JPS5712486A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPS5712486A
JPS5712486A JP8815080A JP8815080A JPS5712486A JP S5712486 A JPS5712486 A JP S5712486A JP 8815080 A JP8815080 A JP 8815080A JP 8815080 A JP8815080 A JP 8815080A JP S5712486 A JPS5712486 A JP S5712486A
Authority
JP
Japan
Prior art keywords
drain
potential
capacity
holding
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8815080A
Other languages
Japanese (ja)
Other versions
JPS6118839B2 (en
Inventor
Masahiko Yoshimoto
Kenji Anami
Osamu Tomizawa
Hiroshi Shinohara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8815080A priority Critical patent/JPS5712486A/en
Publication of JPS5712486A publication Critical patent/JPS5712486A/en
Publication of JPS6118839B2 publication Critical patent/JPS6118839B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G11C11/4125—Cells incorporating circuit means for protecting against loss of information

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To reduce the occurrence of a soft error and increase the noise resistance properties, by connecting the drain of an MOSFET and that of the other MOSFET of a memory cell via a capacity. CONSTITUTION:A drain 18 of an MOSFET10 is connected to a drain 19 of an MOSFET11 via a capacity 23. In the initial state, the potential V1 of the drain 18 is set at a high potential, and the potential of the drain 19 is set at the earth level with a stable holding. In such case, the capacity of drain 18 is equal to the sum of a parasitic capacity 16 and the capacity 23 with a value large enough. Accordingly the degree of level-down is reduced by an injection of the electron grown by an irradiation of alpha-rays or the like for the potential of the drain 18 to avoid an inversion of holding. The capacity 23 shows the same effect even in case the potential of the drain 19 is at a high level with the potential V1 of the drain 18 set at the earth level respectively to avoid an inversion of holding. In such way, the soft error can be reduced.
JP8815080A 1980-06-26 1980-06-26 Semiconductor storage device Granted JPS5712486A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8815080A JPS5712486A (en) 1980-06-26 1980-06-26 Semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8815080A JPS5712486A (en) 1980-06-26 1980-06-26 Semiconductor storage device

Publications (2)

Publication Number Publication Date
JPS5712486A true JPS5712486A (en) 1982-01-22
JPS6118839B2 JPS6118839B2 (en) 1986-05-14

Family

ID=13934896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8815080A Granted JPS5712486A (en) 1980-06-26 1980-06-26 Semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS5712486A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0098417A2 (en) * 1982-06-15 1984-01-18 Kabushiki Kaisha Toshiba Semiconductor memory device
JPS6052998A (en) * 1983-09-02 1985-03-26 Hitachi Ltd Memory cell
JPS6166296A (en) * 1984-09-07 1986-04-05 Nec Corp Complementary mos memory device
JPS61276254A (en) * 1985-05-30 1986-12-06 Nec Corp Mos type semiconductor integrated circuit device
US4858195A (en) * 1986-05-22 1989-08-15 Sony Corporation Bit line charge sensing apparatus having CMOS threshold voltage compensation
US6479860B2 (en) 2000-12-08 2002-11-12 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device
US6597041B2 (en) 2001-01-16 2003-07-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor static random access memory device
US6781869B2 (en) 2002-01-29 2004-08-24 Renesas Technology Corp. Semiconductor memory
US6807081B2 (en) 2001-12-07 2004-10-19 Renesas Technology Corp. Semiconductor memory circuit hard to cause soft error
JP2008052847A (en) * 2006-08-25 2008-03-06 Matsushita Electric Ind Co Ltd Latch circuit, semiconductor integrated circuit provided with the same, sram, flip-flop circuit, information apparatus, communication apparatus, av apparatus, and mobile object

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0098417A2 (en) * 1982-06-15 1984-01-18 Kabushiki Kaisha Toshiba Semiconductor memory device
JPS6052998A (en) * 1983-09-02 1985-03-26 Hitachi Ltd Memory cell
JPS6166296A (en) * 1984-09-07 1986-04-05 Nec Corp Complementary mos memory device
JPS61276254A (en) * 1985-05-30 1986-12-06 Nec Corp Mos type semiconductor integrated circuit device
US4858195A (en) * 1986-05-22 1989-08-15 Sony Corporation Bit line charge sensing apparatus having CMOS threshold voltage compensation
US6479860B2 (en) 2000-12-08 2002-11-12 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device
US6597041B2 (en) 2001-01-16 2003-07-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor static random access memory device
US6807081B2 (en) 2001-12-07 2004-10-19 Renesas Technology Corp. Semiconductor memory circuit hard to cause soft error
US6781869B2 (en) 2002-01-29 2004-08-24 Renesas Technology Corp. Semiconductor memory
JP2008052847A (en) * 2006-08-25 2008-03-06 Matsushita Electric Ind Co Ltd Latch circuit, semiconductor integrated circuit provided with the same, sram, flip-flop circuit, information apparatus, communication apparatus, av apparatus, and mobile object

Also Published As

Publication number Publication date
JPS6118839B2 (en) 1986-05-14

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