JPS6166296A - Complementary mos memory device - Google Patents

Abstract

PURPOSE:To obtain a complementary MOS memory device which is stable to noises by inserting a capacitor between drains of two inverters constituting a MOS memory cell. CONSTITUTION:The 1st layer polysilicone wiring 11 contains a word line and a gate electrode. In addition, the 2nd layer polysilicone wiring 12 is provided together with a VCC dispersion layer wiring 13 and contact holes 14, 14' and 14' respectively. The holes 14' and 14' serve as a GND contact hole and a bit line contact hold respectively. The capacity between both wirings 11 and 12 is used to form a capacitor which is inserted between two inverters, i.e., between nodes 1 and 2. In such a way, a capacitor is put between two inverters by means of the difference between the drain transient answer of a MOS transistor and the gate transient answer. Thus it is possible to obtain a complementary MOS memory device which is stable to noise.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a complementary MOS memory device consisting of six transistors.

(Prior Art) In recent years, the miniaturization of MOS memory devices has progressed, and the amount of information-holding charge in memory cells has been decreasing. Therefore, memory cells are becoming more prone to malfunction due to noise such as alpha rays. Complementary MOS memory devices (hereinafter referred to as 0M0S memory cells) have a structure that is more resistant to noise than other cells, but the above phenomenon is still becoming a real problem.

(Problems to be Solved by the Invention) FIG. 4 is a circuit diagram of a conventional 6-transistor fiOMOs memory cell.

In FIG. 4, Tri and Tr2 are P-channel transistors, and Tr3 to Tr6 are N-channel transistors. Now, assume that node 1 is at high level, ie, Vcc, and node 2 is at low level, ie, GND (ground potential). In this state, the gate voltage of the transistor Trl is GND,
Although the drain voltage is Vcc and a channel region is formed directly under the gate electrode, no current flows because the source-drain voltage is Ov.

On the other hand, the gate voltage of the transistor Tr2 is Vcc.

Drain voltage is GND, V between source and drain
Although a voltage of cc is applied, no current flows because no channel region is formed directly under the gate electrode. now,
A stain flows into node 1 due to noise, and the node 10 level changes from Vcc to G? Tri and Tr2 when falling to JD
Figure 5 (a) and (b) are MOS
Figure 6(a) and (b) are characteristic diagrams for explaining the transient response of the transistor shown in Figures 5(a) and (b). is.

The response of the transistor Tri corresponds to the case where the waveform of the voltage Vcc shown in FIG. 6(a) is applied to the drain of the transistor Tri shown in FIG. 5(a). At this time, the current flowing through Tri is: First, a component due to channel charge discharge flows, and then a normal transistor current flows.The result is schematically shown in FIG. 6(b).

On the other hand, fig It 14 flows through the transistor Tr2.
．． This corresponds to the case where the voltage waveform shown in FIG. 6(a) is applied to the gate of the transistor Tr2 shown in FIG. 85(b)K,
The current flowing from Vcc is first consumed to form the channel region, so as a result, the gate voltage of both transistors Tri and Trz is GND as shown in FIG. 6(b).

Although the drain voltage is GND, the transient current is larger when the channel region is formed in the initial state. Therefore, when node 1 falls from Vcc to GND, node 2
If is below the GND level, the voltage at node 1 increases faster than at node 2. Therefore, due to the amplification effect of the 0M0S memory cell, node 1 rises to the VCC level again, and node 2 rises once, but is discharged by Tr4 and falls to the GND level again.

As explained above, the conventional 6-transistor type 0M0S
Memory has a problem in that it tends to malfunction due to noise.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a complementary MOS memory device that is resistant to noise. Complementary MOS having complementary MOS memory cells consisting of transistors
The MO8 memory device is characterized in that a capacitor is inserted between the drains of two inverters constituting the MO8 memory cell.

(Principle and operation of the invention) Next, the principle and operation of the present invention will be explained.

FIG. 1 is a circuit diagram of an 0M0S memory cell according to the present invention;
FIG. 2 is a characteristic diagram illustrating the transient response of the CMOS memory cell shown in FIG. 1.

The drains of the two inverters constituting the 0MO8 memory cell are node 1.2. A capacitor Ot't- is connected between nodes 1 and 2. Let the capacitance (stray capacitance) of node 1.2 be a, , O,.

Now, node 1 is at high level, electrons due to noise flow into node 1 at high level, and voltage v1 of node 1 becomes Vcc.
Consider the case where the

Because of the N+ drain y-P type substrate (or well) junction of the N-channel transistor, ■ does not become less than -VP (VF is the forward breakdown voltage of the junction and is a positive value). Therefore, v! When decreases from Vcc, ■, ≧V,
It suffices if it holds within the range of V, , V, ≧-VF.

(2) decreases from the initial state Ov, and its value is expressed as. To meet the above conditions, TE1Lij'jL
I o fllt C, Vcc = 5 V, VF = 0.
5 If the V condition is met, V against noise, ,
The response of V is as shown in FIG. 2 due to the transient response characteristics of the MOS transistor explained in FIG. 6 (aL(b)), and Vl and V recover to their original states despite the noise.

A similar equation applies when a noise current flows into (2). Furthermore, the case where the noise current is a Hall current can be handled in almost the same way.

(Example) Next, embodiments of the present invention will be described using the drawings.

FIG. 3 is a plan view of one embodiment of the present invention.

In the WJ3 diagram, 11 is the first layer polysilicon wiring,
This becomes the word line and gate electrode. 12 is second layer polysilicon wiring, 13 is vCC diffusion layer wiring, 4.4', 4" are contact holes, 4' is GND contact hole, 4"
indicates a bit line contact hole. A capacitor inserted between the drains of the two inverters, that is, between nodes 1 and 2, is formed by the interlayer capacitance between the first layer polysilicon wiring 11 and the second layer polysilicon wiring 12. Capacitance 0 consisting of diffusion layer capacitance and transistor gate capacitance
1.0! is set to 20fF (when using the 1.5μ rule, the value is about this value).

It is sufficient if 01g≧zfF. The area of the dish-like 9 parts of the first layer polysilicon wiring 11 and the second layer polysilicon wiring 12 is 10 μm2, and the silicon oxide film between the layers (relative dielectric constant 3
．． If the film thickness of 8) is 1500X, 0□ is 2.24f
F satisfies the above conditions and can exhibit the effects of the present invention. Various other methods of forming inter-nodal capacitance can be considered.

(Effects of the Invention) As explained above, the present invention takes advantage of the difference between the drain transient response and gate transient response of a MOS transistor, and inserts a capacitor between the drains of two inverters, so that noise can be reduced. This has the effect that a stable complementary MOS memory device can be realized.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a complementary MOS memory cell according to the present invention, FIG. 2 is a characteristic diagram illustrating the transient response of the complementary MOS memory cell shown in FIG. 1, and FIG. 3 is a circuit diagram of a complementary MOS memory cell according to an embodiment of the present invention. 4 is a circuit diagram of a conventional 6-transistor type 0M0S memory cell, FIGS. 5(a) and 5(b) are connection diagrams for explaining the transient response of MOS transistors, and FIG.
5a) and 5(b) are characteristic diagrams for explaining the transient response of the MOS transistor shown in FIGS. 5(a) and 5(b). 1.2...Node (inverter drain), 1
1...First layer polysilicon wiring, 12...
...Second layer polysilicon wiring, 13...Vcc
Diffusion layer wiring. 14.14', 14"...Contact hole, Tr
i. Tr2...P channel transistor, Tr3
~Tr6...N-channel transistor. Figure 1 Figure 2 Bullet Figure 3

Claims (1)

[Claims] In a complementary MOS memory device having a complementary MOS memory cell consisting of six transistors, the MOS
A complementary MOS memory device characterized in that a capacitor is inserted between the drains of two inverters constituting a memory cell.