JPS62150765A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain the highly integrated dynamic type semiconductor memory storage having a large information charge accumulation capacitance, a large operational margin and a small chip area by a method wherein capacitance between polycrystalline silicons is formed in a grooved isolation region, and an opposing electrode type 2-cell/1- bit structure is integrated together with a folding type bit wire structure. CONSTITUTION:An N<+> type diffusion layer 5 is formed in a suitable region on a P-type silicon substrate 1, and this N<+> type diffusion layer 5 becomes the source and drain region of the gate transistor of each memory cell. The P-type silicon substrate, located between the N<+> type diffusion layer 5 constituting the drain region is formed and the N<+> type diffusion layer 5 constituting the source region, forms the channel region 11 of the transistor. A grooved isolation region 17 is formed on the circumference of the N<+> type diffusion layer 5 and the channel region 11, and a pair of opposing electrodes 12 and 13 are opposingly formed in the grooved isolation region 17 leading the prescribed space between them. A memory cell capacitor, namely, an information charge accumulation capacitor is formed with said opposing electrodes 12 and 13 and the capacitor insulating film 14 located between the electrodes 12 and 13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a memory cell configuration suitable for high integration of semiconductor memory devices.

[Prior Art] Figures 3A and 3B are, for example, lecture numbers @FAM1 of the International Solid State Circuits Conference 1 (ISSCC85) in 1985.
7.4 is a diagram showing a highly integrated dynamic semiconductor memory device proposed in 7.4.

Furthermore, Fig. 3A shows the plan view, and Fig. 3B shows the plan view of Fig. 3A.
FIG. 3 shows a cross-sectional view along line X-X- in the figure.

In the figure, on a P-type substrate 1, an N" type diffusion layer 5, a field oxide film 2, a first polycrystalline silicon layer 3, a second polycrystalline silicon layer 117, a first AQ wiring layer 6, a first An insulating film 9 and the like are laminated between the AQ wirings !18 and 11 of No.2.

The first AfL wiring Fm6 serves as a bit line, and is electrically connected to the N+ type scattering layer 5 via the contact hole 10. The second polycrystalline silicon layer 7 serves as a word line, and is short-circuited at regular intervals by second AQ interconnections 8 to reduce its resistance.

Here, a trench isolation region is formed around the memory cell MC. Utilizing the side surface of this grooved isolation region, an information charge storage capacitor Cr is formed by the first polycrystalline silicon layer 3, the capacitor insulation B104 (a part of the field oxide 12), and the N1 type diffusion layer 5. ing. Furthermore, the flat portion of the memory cell MC has a similar structure, and has an information charge storage capacity f!
k Cr is formed. In this way, if the grooved isolation part on the outer periphery of the memory cell MC is utilized as an information charge storage capacitor, sufficient operating margin can be achieved even if the chip area is reduced and the area of the flat part forming the capacitor I Cr is reduced. Accordingly, it is possible to obtain a semiconductor memory device which has a wide range of information charges and can secure a sufficient information charge capacity.

[Problems to be Solved by the Invention] By the way, the above-mentioned conventional structure in which an information charge storage region is formed in the grooved isolation region is disclosed in, for example, Japanese Patent Application Laid-Open No. 51-7.
When applied to the folded bit line configuration shown in Japanese Patent No. 4535, the cross-sectional structure along Y-Y'' in FIG. 3A becomes as shown in FIG. 4. In the structure shown in FIG. N+ that constitutes one electrode of the charge storage capacitor
Since the type scattering layer 5 is formed directly on the p-type substrate 1, the contact area between the information charge storage capacitor and the p-type substrate 1 is widened, and as a result, the fractional carriers ( LM where electron-hole pairs) are easily collected in the charge storage capacitor
It is 31. Therefore, there is a problem in that the information stored in the memory cell is susceptible to noise errors, and the structure is not very effective in terms of resistance to soft 1-errors.

This invention was made in order to solve the above-mentioned problems, and even when the number of #4 stacks is high, it is possible to secure an information storage charge vehicle, and to minimize the influence of injection of minority carriers by α particles, etc. It is an object of the present invention to provide a highly integrated dynamic semiconductor memory device that can reduce the amount of data required.

[Means for solving the frontage point] A semiconductor memory device according to the present invention has a folded bit p
In IM formation, a trench isolation region is formed between a first memory cell belonging to one bit line of a pair of bit lines for one sense amplifier and a second memory cell belonging to the other bit line. However, a memory cell capacitor is formed within this n-drilled isolation region, and this one memory cell capacitor is shared by the first and second memory cells.

[Function] In the semiconductor memory device of the present invention, since the memory cell capacitor is formed in the trench isolation region between the memory cell regions, the flat area of the chip can be reduced, and the chip can be highly integrated. . Furthermore, memory cells belonging to one pair of folded bit lines and memory cells belonging to the other pair share one memory cell capacity, and these two
One memory cell constitutes one bit, so even if noise occurs on only one side of the memory cells that share the memory cell capacity, the same noise will always be applied to both memory cells via the memory cell capacity. Since this is noise, the data is not affected by noise at all.

[Embodiment] FIGS. 1A and 1B are diagrams showing a semiconductor memory device according to an embodiment of the present invention, in particular, FIG. Figure 3 shows a cross-sectional view along line X-X-. In the figure, an N+ type diffusion dowel 5 is formed on a P type silicon substrate 1 in an appropriate region. This N+ type scattering layer 5 becomes the source and drain regions 4 of the gate transistor of each memory cell. The P-type silicon substrate 1 between the N+ type extension gjJ5 forming the train region and the N+ type extension 11[5 forming the source region forms the channel region 11 of the transistor. A word line polycrystalline silicon layer 15 is formed so as to pass over this channel region 11 . Aluminum wiring 6, which becomes a bit line, is formed perpendicular to word line 15. Here, the two bit lines 6 shown in FIG. 1A constitute so-called folded bit lines BL, BL. Therefore, these bits KABL, BL are connected to the same sense amplifier (not shown). A plurality of memory cells are formed in pairs along these bit lines BL, BL, respectively. The lines P1 to BL are electrically connected to the source or drain regions of the gate transistors of the memory cells belonging thereto via contact holes 10. Similarly, the bit line Bπ is electrically connected to the source or drain region of the gate transistor of the memory cell to which it belongs via the contact hole 10.

Here, trench isolation regions 17 are formed around N++ diffusion 15 and channel region 11.

A pair of opposing electrodes 12 and 13 are formed inside this grooved isolation region 17 and facing each other with a predetermined interval. These opposing electrodes 12 and 13 and the capacitor insulator 114 between them form a memory cell capacity, that is, an information charge storage capacity. The counter electrode 12 is the contact hole 1
6 to the bit line B and to the source or drain region of the gate transistor of the memory cell. The counter electrode 13 is connected to the contact 1 via a hole 16 to the source or drain region of the gate transistor of the memory cell that extends to the bit line BL.

Therefore, one memory cell belonging to the bit line BL and one memory cell belonging to the bit line BL share one information charge storage capacity.

What should be noted here is that the two memory cells that share one information charge storage capacity are the bit line BL.

-10- [Above, they form a pair, each gate transistor being controlled by the same word line.

Although FIG. 1A shows a partial configuration of the memory cell array, in an actual memory cell array, a large number of word lines and folded pit line pairs are formed, whereby memory cells are arranged in a matrix.

In the semiconductor memory device with the above configuration, the information charge storage capacity is formed within the trench isolation region, so even if the flat area of the chip is reduced, sufficient information charge storage capacity can be secured, and as a result, the chip High integration can be achieved. In addition, since the opposing electrodes 12 and 13 are formed so as not to contact the side walls of the trench + m region 17, the contact area between the information charge storage capacitor and the P-type substrate 1 can be minimized. As a result, it is possible to reduce the injection of minority carriers generated within the substrate by α particles and the like into the information charge storage capacitor. Therefore, the occurrence of soft errors can be reduced.

FIG. 2 is an equivalent circuit diagram of the semiconductor memory device shown in FIGS. 1A and 1B. As shown in the figure, the gate transistor T of the memory cell belonging to the bit line BL is connected to one end of the information charge storage capacitor C.

Further, the gate transistor T- of the memory cell belonging to the bit line (2) is connected to the narrow end of the information charge storage capacitor iiC.

Note that the gate transistors T and T- form a pair, and their on/off is controlled by the same word line WL. As is clear from FIG. 2, bit line B
The memory cells belonging to L and the memory cells belonging to bit line BL share one information charge storage capacitor IC and constitute one hit. That is, two memory cells constitute one bit. This 2-self, 71-bit configuration has the following advantages.

(2) Complementary signals are always read out to the bit line pair, eliminating the need for dummy cells. Therefore, the group L of the dummy cell
1! There is no need to consider voltage fluctuations.

(2) When reading information charges to the bit line, successive signal voltage differences can always be read with the maximum width, regardless of the precharge voltage of the bit line.

■ Noise voltages such as power supply voltage fluctuations and substrate voltage fluctuations always become a common mode and are coupled to the memory cells, so the operating margin remains unchanged for either high or low information.

■ From the advantages mentioned in ■, ■, and ■ above, when trying to secure the same operating margin as conventional semiconductor memory devices,
The values of the information charge storage volumes forming the pair can each be reduced to 1/2 or less of those of the conventional structure, making it possible to reduce the size of the memory cell array section.

Furthermore, in the configuration of the above embodiment, two memory cells have one
Since the memory cell capacity is shared, even if noise is added to only one memory cell due to noise caused by α particles, it will always become common noise and will be coupled to the other memory cell, so the operating margin will not change at all.

As mentioned above, by forming the polycrystalline silicon interlayer in the trench isolation filter, and combining the opposing electrode type 2 cells/1 pin 1 to 1 to 2 cells with the folded bit line configuration, the information charge A high-convergence dynamic semiconductor memory device having a large storage capacity, a wide operating margin, and a small chip area can be obtained.

[Effects of the Invention] As described above, according to the present invention, a trench isolation region is formed between each of the memory cells forming a pair on a folded line pair. A memory cell array with a 2-cell/'1-bit configuration is realized by forming a memory capacity in the memory cell and sharing this memory capacity n with the memory cell on one pin 1-line and the memory cell on the curved pin 1-line. Therefore, it is possible to obtain a highly integrated semiconductor memory device with a wide operating margin and high reliability against soft errors and the like.

[Brief explanation of drawings]

FIGS. 1A and 1B are a plan view and a sectional view showing a semiconductor memory device according to an embodiment of the present invention. FIG. 2 is an equivalent circuit diagram of the semiconductor memory device shown in FIGS. 1A and 1B. 3A, 3B, and 4 are a plan view and a sectional view showing a conventional semiconductor memory device U. In the figure, 1 is a P-type silicon substrate, 5 is an N+ type scattered layer 6 is an ArL wiring that becomes a bit line, 10 is a contact hole, 11 is a channel of a transistor, 12 and 13
14 is a counter electrode, 14 is a capacitor insulating film, 15 is a polycrystalline silicon layer that becomes a word line, 16 is a contact hole, 1
7 indicates a grooved separation area. In addition. The same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa 1st A
Figure 4

Claims (3)

[Claims] (1) A semiconductor memory device with a folded bit line configuration in which adjacent bit lines form a pair with respect to one sense amplifier, in which the semiconductor memory device has a folded bit line configuration in which adjacent bit lines form a pair with respect to one sense amplifier; a first memory cell having a gate transistor formed and connected to the bit line; and a first memory cell formed to belong to the other bit line of the pair of bit lines and connected to the bit line. a second memory cell having a gate transistor; and a region between the first memory cell and the second memory cell, each gate transistor of which is controlled by the same word line and located in an adjacent positional relationship. a trench isolation region formed; a memory cell capacitor formed in the trench isolation region; means for connecting one electrode of the memory cell capacitor to the gate transistor of the first memory cell; and means for connecting the other electrode of the cell capacitance to the gate transistor of the second memory cell, the first memory cell and the second memory cell sharing the memory cell capacitance to form one bit. A semiconductor memory device comprising a memory cell array in which a plurality of sets of two memory cells each having a 1-bit configuration are arranged. (2) The semiconductor memory device according to claim 1, wherein at least one of one electrode and the other electrode of the memory cell capacitor is formed on a side surface of the trench isolation region. (3) The semiconductor memory device according to claim 1, wherein the memory cell capacitor is formed so that neither one electrode nor the other electrode is in contact with a side surface of the trench isolation region.