JPS57114925A - Hold control system - Google Patents

Hold control system

Info

Publication number
JPS57114925A
JPS57114925A JP56000146A JP14681A JPS57114925A JP S57114925 A JPS57114925 A JP S57114925A JP 56000146 A JP56000146 A JP 56000146A JP 14681 A JP14681 A JP 14681A JP S57114925 A JPS57114925 A JP S57114925A
Authority
JP
Japan
Prior art keywords
controller
transfer
processor
microprocessor
data bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56000146A
Other languages
English (en)
Inventor
Masao Suga
Akira Tokunaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56000146A priority Critical patent/JPS57114925A/ja
Publication of JPS57114925A publication Critical patent/JPS57114925A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/285—Halt processor DMA

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
  • Bus Control (AREA)
JP56000146A 1981-01-06 1981-01-06 Hold control system Pending JPS57114925A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56000146A JPS57114925A (en) 1981-01-06 1981-01-06 Hold control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56000146A JPS57114925A (en) 1981-01-06 1981-01-06 Hold control system

Publications (1)

Publication Number Publication Date
JPS57114925A true JPS57114925A (en) 1982-07-17

Family

ID=11465885

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56000146A Pending JPS57114925A (en) 1981-01-06 1981-01-06 Hold control system

Country Status (1)

Country Link
JP (1) JPS57114925A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6019269A (ja) * 1983-07-13 1985-01-31 Nec Corp 高速デ−タ転送方式
JPS6392966U (ja) * 1986-12-08 1988-06-15

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6019269A (ja) * 1983-07-13 1985-01-31 Nec Corp 高速デ−タ転送方式
JPH0133861B2 (ja) * 1983-07-13 1989-07-17 Nippon Electric Co
JPS6392966U (ja) * 1986-12-08 1988-06-15

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