JPS57113253A - Method of forming dielectric insulating region in single crystal silicon substrate - Google Patents

Method of forming dielectric insulating region in single crystal silicon substrate

Info

Publication number
JPS57113253A
JPS57113253A JP56179098A JP17909881A JPS57113253A JP S57113253 A JPS57113253 A JP S57113253A JP 56179098 A JP56179098 A JP 56179098A JP 17909881 A JP17909881 A JP 17909881A JP S57113253 A JPS57113253 A JP S57113253A
Authority
JP
Japan
Prior art keywords
single crystal
silicon substrate
crystal silicon
insulating region
dielectric insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56179098A
Other languages
English (en)
Other versions
JPS6142423B2 (ja
Inventor
Raizuman Jieikobu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS57113253A publication Critical patent/JPS57113253A/ja
Publication of JPS6142423B2 publication Critical patent/JPS6142423B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
JP56179098A 1980-12-19 1981-11-10 Method of forming dielectric insulating region in single crystal silicon substrate Granted JPS57113253A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/218,155 US4356211A (en) 1980-12-19 1980-12-19 Forming air-dielectric isolation regions in a monocrystalline silicon substrate by differential oxidation of polysilicon

Publications (2)

Publication Number Publication Date
JPS57113253A true JPS57113253A (en) 1982-07-14
JPS6142423B2 JPS6142423B2 (ja) 1986-09-20

Family

ID=22813976

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56179098A Granted JPS57113253A (en) 1980-12-19 1981-11-10 Method of forming dielectric insulating region in single crystal silicon substrate

Country Status (4)

Country Link
US (1) US4356211A (ja)
EP (1) EP0054659B1 (ja)
JP (1) JPS57113253A (ja)
DE (1) DE3164903D1 (ja)

Cited By (4)

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Publication number Priority date Publication date Assignee Title
JPS59172246A (ja) * 1983-03-18 1984-09-28 Seiko Instr & Electronics Ltd 凹部分離半導体装置とその製造方法
JPH1116998A (ja) * 1997-06-20 1999-01-22 Samsung Electron Co Ltd ボイドを有するトレンチ素子分離膜形成方法
US6518144B2 (en) 2000-10-10 2003-02-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having trenches and process for same
JP2017011311A (ja) * 2016-10-13 2017-01-12 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

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US4407058A (en) * 1981-05-22 1983-10-04 International Business Machines Corporation Method of making dense vertical FET's
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US4544576A (en) * 1981-07-27 1985-10-01 International Business Machines Corporation Deep dielectric isolation by fused glass
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US4597164A (en) * 1984-08-31 1986-07-01 Texas Instruments Incorporated Trench isolation process for integrated circuit devices
US4573257A (en) * 1984-09-14 1986-03-04 Motorola, Inc. Method of forming self-aligned implanted channel-stop and buried layer utilizing non-single crystal alignment key
US4583282A (en) * 1984-09-14 1986-04-22 Motorola, Inc. Process for self-aligned buried layer, field guard, and isolation
US4574469A (en) * 1984-09-14 1986-03-11 Motorola, Inc. Process for self-aligned buried layer, channel-stop, and isolation
US4656497A (en) * 1984-11-01 1987-04-07 Ncr Corporation Trench isolation structures
US4571819A (en) * 1984-11-01 1986-02-25 Ncr Corporation Method for forming trench isolation structures
US4604150A (en) * 1985-01-25 1986-08-05 At&T Bell Laboratories Controlled boron doping of silicon
US4744863A (en) * 1985-04-26 1988-05-17 Wisconsin Alumni Research Foundation Sealed cavity semiconductor pressure transducers and method of producing the same
WO1986006548A1 (en) * 1985-04-26 1986-11-06 Wisconsin Alumni Research Foundation Sealed cavity semiconductor pressure transducers and method
US4853669A (en) * 1985-04-26 1989-08-01 Wisconsin Alumni Research Foundation Sealed cavity semiconductor pressure transducers and method of producing the same
US4685196A (en) * 1985-07-29 1987-08-11 Industrial Technology Research Institute Method for making planar FET having gate, source and drain in the same plane
US4666556A (en) * 1986-05-12 1987-05-19 International Business Machines Corporation Trench sidewall isolation by polysilicon oxidation
JPH07105436B2 (ja) * 1986-07-18 1995-11-13 株式会社東芝 半導体装置の製造方法
US5098856A (en) * 1991-06-18 1992-03-24 International Business Machines Corporation Air-filled isolation trench with chemically vapor deposited silicon dioxide cap
JP2776457B2 (ja) * 1992-12-29 1998-07-16 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体デバイスのクラックストップ形成方法及び半導体デバイス
US5516720A (en) * 1994-02-14 1996-05-14 United Microelectronics Corporation Stress relaxation in dielectric before metallization
JPH07326659A (ja) 1994-06-02 1995-12-12 Hitachi Ltd 半導体集積回路装置の製造方法
JPH09172061A (ja) * 1995-12-18 1997-06-30 Fuji Electric Co Ltd 半導体装置の製造方法
US6064104A (en) * 1996-01-31 2000-05-16 Advanced Micro Devices, Inc. Trench isolation structures with oxidized silicon regions and method for making the same
US5780347A (en) * 1996-05-20 1998-07-14 Kapoor; Ashok K. Method of forming polysilicon local interconnects
US5757059A (en) * 1996-07-30 1998-05-26 International Business Machines Corporation Insulated gate field effect transistor
US5824580A (en) * 1996-07-30 1998-10-20 International Business Machines Corporation Method of manufacturing an insulated gate field effect transistor
US5721448A (en) * 1996-07-30 1998-02-24 International Business Machines Corporation Integrated circuit chip having isolation trenches composed of a dielectric layer with oxidation catalyst material
US5926717A (en) * 1996-12-10 1999-07-20 Advanced Micro Devices, Inc. Method of making an integrated circuit with oxidizable trench liner
KR100234408B1 (ko) * 1997-02-17 1999-12-15 윤종용 반도체장치의 소자분리방법
JP3389075B2 (ja) * 1997-10-01 2003-03-24 株式会社東芝 半導体装置の製造方法
KR100252866B1 (ko) * 1997-12-13 2000-04-15 김영환 반도체소자 및 이의 제조방법
US6376893B1 (en) 1997-12-13 2002-04-23 Hyundai Electronics Industries Co., Ltd. Trench isolation structure and fabrication method thereof
US6140691A (en) * 1997-12-19 2000-10-31 Advanced Micro Devices, Inc. Trench isolation structure having a low K dielectric material isolated from a silicon-based substrate
US5882983A (en) * 1997-12-19 1999-03-16 Advanced Micro Devices, Inc. Trench isolation structure partially bound between a pair of low K dielectric structures
US6153482A (en) * 1998-10-16 2000-11-28 Nanya Technology Corp. Method for fabricating LOCOS isolation having a planar surface which includes having the polish stop layer at a lower level than the LOCOS formation
KR100312943B1 (ko) * 1999-03-18 2001-11-03 김영환 반도체장치 및 그의 제조방법
US6159840A (en) * 1999-11-12 2000-12-12 United Semiconductor Corp. Fabrication method for a dual damascene comprising an air-gap
KR100327348B1 (en) 2000-07-26 2002-03-06 Samsung Electronics Co Ltd Semiconductor capable of decreasing junction leakage current and narrow width effect and fabricating method thereof
FR2830984B1 (fr) * 2001-10-17 2005-02-25 St Microelectronics Sa Tranchee d'isolement et procede de realisation
JP2003158180A (ja) * 2001-11-26 2003-05-30 Mitsubishi Electric Corp トレンチ分離を有する半導体装置およびその製造方法
US6791155B1 (en) * 2002-09-20 2004-09-14 Integrated Device Technology, Inc. Stress-relieved shallow trench isolation (STI) structure and method for forming the same
JP4922753B2 (ja) * 2003-03-20 2012-04-25 パナソニック株式会社 半導体装置およびその製造方法
JP2005142481A (ja) * 2003-11-10 2005-06-02 Nec Electronics Corp 半導体装置の製造方法
JP2005150522A (ja) * 2003-11-18 2005-06-09 Toshiba Corp 半導体装置及びその製造方法
KR100538810B1 (ko) * 2003-12-29 2005-12-23 주식회사 하이닉스반도체 반도체소자의 소자분리 방법
KR100688547B1 (ko) * 2005-05-18 2007-03-02 삼성전자주식회사 Ｓｔｉ 구조를 가지는 반도체 소자 및 그 제조 방법
US20070235783A9 (en) * 2005-07-19 2007-10-11 Micron Technology, Inc. Semiconductor constructions, memory arrays, electronic systems, and methods of forming semiconductor constructions
US7772672B2 (en) 2005-09-01 2010-08-10 Micron Technology, Inc. Semiconductor constructions
US20070212874A1 (en) * 2006-03-08 2007-09-13 Micron Technology, Inc. Method for filling shallow isolation trenches and other recesses during the formation of a semiconductor device and electronic systems including the semiconductor device
US7799694B2 (en) 2006-04-11 2010-09-21 Micron Technology, Inc. Methods of forming semiconductor constructions
US7656003B2 (en) * 2006-08-25 2010-02-02 Hvvi Semiconductors, Inc Electrical stress protection apparatus and method of manufacture
DE102007004320A1 (de) * 2007-01-29 2008-07-31 Infineon Technologies Ag Halbleiterbauelement mit vertikalen Strukturen von hohem Aspektverhältnis und Verfahren zur Herstellung einer kapazitiven Struktur in einem Halbleiterkörper
JP2009044000A (ja) * 2007-08-09 2009-02-26 Toshiba Corp 不揮発性半導体メモリ及びその製造方法
DE102007052820A1 (de) * 2007-11-06 2009-05-14 Austriamicrosystems Ag Verfahren zur Herstellung eines Isolationsgrabens in einem Halbleitersubstrat und Halbleiterbauelement mit einem Isolationsgraben
US7811896B2 (en) * 2007-12-11 2010-10-12 Hvvi Semiconductors, Inc. Semiconductor structure and method of manufacture
JP2009147000A (ja) * 2007-12-12 2009-07-02 Seiko Instruments Inc 半導体装置の製造方法
US8471346B2 (en) * 2009-02-27 2013-06-25 Infineon Technologies Ag Semiconductor device including a cavity
EP2454398A2 (en) * 2009-07-16 2012-05-23 MEMC Singapore Pte. Ltd. Coated crucibles and methods for preparing and use thereof
KR102057340B1 (ko) 2013-03-29 2019-12-19 매그나칩 반도체 유한회사 반도체 소자 및 그 제조방법
CN106409748B (zh) 2015-08-03 2020-11-17 联华电子股份有限公司 半导体元件及其制作方法
US9660022B2 (en) 2015-08-20 2017-05-23 United Microelectronics Corp. Semiconductive device with a single diffusion break and method of fabricating the same

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US3874920A (en) * 1973-06-28 1975-04-01 Ibm Boron silicide method for making thermally oxidized boron doped poly-crystalline silicon having minimum resistivity
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US4104086A (en) * 1977-08-15 1978-08-01 International Business Machines Corporation Method for forming isolated regions of silicon utilizing reactive ion etching
US4140558A (en) * 1978-03-02 1979-02-20 Bell Telephone Laboratories, Incorporated Isolation of integrated circuits utilizing selective etching and diffusion
US4196440A (en) * 1978-05-25 1980-04-01 International Business Machines Corporation Lateral PNP or NPN with a high gain
US4264382A (en) * 1978-05-25 1981-04-28 International Business Machines Corporation Method for making a lateral PNP or NPN with a high gain utilizing reactive ion etching of buried high conductivity regions
US4256514A (en) * 1978-11-03 1981-03-17 International Business Machines Corporation Method for forming a narrow dimensioned region on a body
US4238278A (en) * 1979-06-14 1980-12-09 International Business Machines Corporation Polycrystalline silicon oxidation method for making shallow and deep isolation trenches

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59172246A (ja) * 1983-03-18 1984-09-28 Seiko Instr & Electronics Ltd 凹部分離半導体装置とその製造方法
JPH1116998A (ja) * 1997-06-20 1999-01-22 Samsung Electron Co Ltd ボイドを有するトレンチ素子分離膜形成方法
US6518144B2 (en) 2000-10-10 2003-02-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having trenches and process for same
JP2017011311A (ja) * 2016-10-13 2017-01-12 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

Also Published As

Publication number Publication date
DE3164903D1 (en) 1984-08-23
US4356211A (en) 1982-10-26
JPS6142423B2 (ja) 1986-09-20
EP0054659A1 (en) 1982-06-30
EP0054659B1 (en) 1984-07-18

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