JPS57109027A - Contention controlling system - Google Patents

Contention controlling system

Info

Publication number
JPS57109027A
JPS57109027A JP18690580A JP18690580A JPS57109027A JP S57109027 A JPS57109027 A JP S57109027A JP 18690580 A JP18690580 A JP 18690580A JP 18690580 A JP18690580 A JP 18690580A JP S57109027 A JPS57109027 A JP S57109027A
Authority
JP
Japan
Prior art keywords
access
bus
level
attained
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18690580A
Other languages
Japanese (ja)
Inventor
Kanzo Noda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18690580A priority Critical patent/JPS57109027A/en
Publication of JPS57109027A publication Critical patent/JPS57109027A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To improve the processing efficiency of a system by processing the acceptance of access requests without giving priority to any request even if access requests from an external and an internal bus conflict with each other in the internal register of a channel device. CONSTITUTION:When access from an internal bus 13 to a register 6 is attained, an access request signal SL sent from a internal bus controlling circuit has a level ''1''. Therefore, even if an access request is sent from a common bus 2 side, an NAND circui 16 stops an access request signal Ri. Then when the access from the bus 13 to the register 16 ends, the level of the signal SL decreases to a ''0'', so the selection signal ST of the output side of the circuit 16 has a level ''1''. Consequently, access from the common bus 2 side is attained. When access from the internal bus 13 is attained during the access from the bus 2 to the contrary, an FF23 is reset and a synchronizing signal A has a level ''0'' to reset a synchronizing signal SL2 normally, so that access from the bus 13 is attained.
JP18690580A 1980-12-26 1980-12-26 Contention controlling system Pending JPS57109027A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18690580A JPS57109027A (en) 1980-12-26 1980-12-26 Contention controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18690580A JPS57109027A (en) 1980-12-26 1980-12-26 Contention controlling system

Publications (1)

Publication Number Publication Date
JPS57109027A true JPS57109027A (en) 1982-07-07

Family

ID=16196727

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18690580A Pending JPS57109027A (en) 1980-12-26 1980-12-26 Contention controlling system

Country Status (1)

Country Link
JP (1) JPS57109027A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5128731A (en) * 1974-09-04 1976-03-11 Tokyo Shibaura Electric Co
JPS5483726A (en) * 1977-12-16 1979-07-04 Fujitsu Ltd Memory access processing system of data processing system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5128731A (en) * 1974-09-04 1976-03-11 Tokyo Shibaura Electric Co
JPS5483726A (en) * 1977-12-16 1979-07-04 Fujitsu Ltd Memory access processing system of data processing system

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