JPS57101955A - Status history storage system - Google Patents

Status history storage system

Info

Publication number
JPS57101955A
JPS57101955A JP55177907A JP17790780A JPS57101955A JP S57101955 A JPS57101955 A JP S57101955A JP 55177907 A JP55177907 A JP 55177907A JP 17790780 A JP17790780 A JP 17790780A JP S57101955 A JPS57101955 A JP S57101955A
Authority
JP
Japan
Prior art keywords
storage
instruction
maximum frequency
internal state
status history
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55177907A
Other languages
English (en)
Inventor
Shinichi Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55177907A priority Critical patent/JPS57101955A/ja
Publication of JPS57101955A publication Critical patent/JPS57101955A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
JP55177907A 1980-12-16 1980-12-16 Status history storage system Pending JPS57101955A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55177907A JPS57101955A (en) 1980-12-16 1980-12-16 Status history storage system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55177907A JPS57101955A (en) 1980-12-16 1980-12-16 Status history storage system

Publications (1)

Publication Number Publication Date
JPS57101955A true JPS57101955A (en) 1982-06-24

Family

ID=16039140

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55177907A Pending JPS57101955A (en) 1980-12-16 1980-12-16 Status history storage system

Country Status (1)

Country Link
JP (1) JPS57101955A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5810249A (ja) * 1981-07-13 1983-01-20 Nec Corp 状態履歴記憶方式
JPS59180759A (ja) * 1983-03-31 1984-10-13 Fujitsu Ltd ヒストリメモリの制御方式
FR2946815A1 (fr) * 2009-06-12 2010-12-17 Thales Sa Procede d'acquisition d'une pluralite de signaux logiques, avec confirmation de validite d'etat

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5810249A (ja) * 1981-07-13 1983-01-20 Nec Corp 状態履歴記憶方式
JPS59180759A (ja) * 1983-03-31 1984-10-13 Fujitsu Ltd ヒストリメモリの制御方式
FR2946815A1 (fr) * 2009-06-12 2010-12-17 Thales Sa Procede d'acquisition d'une pluralite de signaux logiques, avec confirmation de validite d'etat
US8095843B2 (en) 2009-06-12 2012-01-10 Thales Method of acquiring a plurality of logic signals, with confirmation of state validity

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