JPS5725054A - Memory access control system - Google Patents

Memory access control system

Info

Publication number
JPS5725054A
JPS5725054A JP10018580A JP10018580A JPS5725054A JP S5725054 A JPS5725054 A JP S5725054A JP 10018580 A JP10018580 A JP 10018580A JP 10018580 A JP10018580 A JP 10018580A JP S5725054 A JPS5725054 A JP S5725054A
Authority
JP
Japan
Prior art keywords
memory access
request
access request
urgency
intensity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10018580A
Other languages
Japanese (ja)
Inventor
Yoshinori Chiwaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10018580A priority Critical patent/JPS5725054A/en
Publication of JPS5725054A publication Critical patent/JPS5725054A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Abstract

PURPOSE:To diminish a data loss or an overrun fault in an input/output device system, by executing a memory access in order of a memory access request whose degree of urgency is high, in accordance with intensity of the request. CONSTITUTION:When a memory access request is stored in a memory access request stack 53 by adding a subtraction counter 54 by which subtraction is executed at constant time intervals, intensity of the request is also stored in the subtraction counter 54 as time information, and in case when the next memory cycle is assigned, a memory access request corresponding to minimum contents of the time information of the subtraction counter 54 is selected, and a memory device 4 is accessed. Accordingly, the degree of urgency is indicated by a waiting allowable time interval information, is subtracted at constant time intervals, and the memory access is executed in order from the minimum request, therefore, in accordance with intensity of a request, the memory access is executed in order of a memory access request whose degree of urgency is high.
JP10018580A 1980-07-22 1980-07-22 Memory access control system Pending JPS5725054A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10018580A JPS5725054A (en) 1980-07-22 1980-07-22 Memory access control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10018580A JPS5725054A (en) 1980-07-22 1980-07-22 Memory access control system

Publications (1)

Publication Number Publication Date
JPS5725054A true JPS5725054A (en) 1982-02-09

Family

ID=14267241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10018580A Pending JPS5725054A (en) 1980-07-22 1980-07-22 Memory access control system

Country Status (1)

Country Link
JP (1) JPS5725054A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006163711A (en) * 2004-12-06 2006-06-22 Renesas Technology Corp Information processing system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006163711A (en) * 2004-12-06 2006-06-22 Renesas Technology Corp Information processing system
US7873796B2 (en) 2004-12-06 2011-01-18 Renesas Electronics Corporation Information processor system
US8429355B2 (en) 2004-12-06 2013-04-23 Renesas Electronics Corporation Information processor system
US8621158B2 (en) 2004-12-06 2013-12-31 Renesas Electronics Corporation Information processor system

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