JPS5696848A - Forming method for low resistor of hybrid integrated circuit - Google Patents

Forming method for low resistor of hybrid integrated circuit

Info

Publication number
JPS5696848A
JPS5696848A JP10746779A JP10746779A JPS5696848A JP S5696848 A JPS5696848 A JP S5696848A JP 10746779 A JP10746779 A JP 10746779A JP 10746779 A JP10746779 A JP 10746779A JP S5696848 A JPS5696848 A JP S5696848A
Authority
JP
Japan
Prior art keywords
film
covered
resistor
copper foil
path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10746779A
Other languages
Japanese (ja)
Inventor
Akira Kazami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP10746779A priority Critical patent/JPS5696848A/en
Publication of JPS5696848A publication Critical patent/JPS5696848A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/702Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
    • H01L21/707Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof of thin-film circuits or parts thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain the low resistance resistor having large electric power capacity by covering an insulating layer on a good thermal conductive metal substrate, forming a conductive path thereon, covering the edge of the path with a mask and forming an Ni-plated layer from the end of the path to the exposed part of the insulating layer. CONSTITUTION:An Al2O3 film 3 as an insulator is formed on an aluminum substrate having good thermal conductivity, and a copper foil 4 is bonded through an adhesive resin 3 thereon. Then, the copper foil 4 is etched to a predetermined pattern with a solution such as ferric chloride or the like, a conductive path 4 formed of the copper foil 4 is thus formed, a resist film 6 is covered on the part except the resistor forming part and exposed rough Al2O3 film 2, the part covered with no film 6 is activated, and Ni may be easily adhered. Thereafter, Ni-plating is conducted, Ni low resistance resistor 7 is formed on the part covered with no film 6, the film 6 is removed together with the Ni covered on the edge, and the resistor 7 of predetermined shape is thus formed.
JP10746779A 1979-08-22 1979-08-22 Forming method for low resistor of hybrid integrated circuit Pending JPS5696848A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10746779A JPS5696848A (en) 1979-08-22 1979-08-22 Forming method for low resistor of hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10746779A JPS5696848A (en) 1979-08-22 1979-08-22 Forming method for low resistor of hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS5696848A true JPS5696848A (en) 1981-08-05

Family

ID=14459927

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10746779A Pending JPS5696848A (en) 1979-08-22 1979-08-22 Forming method for low resistor of hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS5696848A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS423717Y1 (en) * 1965-08-05 1967-03-03
JPS4525826Y1 (en) * 1967-11-29 1970-10-07
JPS5423427A (en) * 1977-07-25 1979-02-22 Toshiba Corp Beam index television picture receiver

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS423717Y1 (en) * 1965-08-05 1967-03-03
JPS4525826Y1 (en) * 1967-11-29 1970-10-07
JPS5423427A (en) * 1977-07-25 1979-02-22 Toshiba Corp Beam index television picture receiver

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