JPS5629358A - Manufacture of hybrid integrated circuit - Google Patents

Manufacture of hybrid integrated circuit

Info

Publication number
JPS5629358A
JPS5629358A JP10541879A JP10541879A JPS5629358A JP S5629358 A JPS5629358 A JP S5629358A JP 10541879 A JP10541879 A JP 10541879A JP 10541879 A JP10541879 A JP 10541879A JP S5629358 A JPS5629358 A JP S5629358A
Authority
JP
Japan
Prior art keywords
path
resistor
plated layer
hybrid
coated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10541879A
Other languages
Japanese (ja)
Inventor
Akira Kazami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP10541879A priority Critical patent/JPS5629358A/en
Publication of JPS5629358A publication Critical patent/JPS5629358A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/702—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
    • H01L21/707—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof of thin-film circuits or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To obtain a hybrid IC durable for large electric power by simultaneously forming an Ni plated layer secured with a lead wire and a low resistor. CONSTITUTION:An Al2O3 layer 2 is formed on one surface of aluminum plate 1, and a copper foil roughed on the back surface is bonded thereto with insulating resin 3. When the copper foil is etched to form an electroconductive path 4, rough surface 5 is formed on the surface of the resin 3. A resist mask 7 is coated thereon, an activator is coated thereon, and an Ni-plated layer 7 an Ni-low resistor 8 are formed thereon by an electroless plating process. The plating conditions are suitably selected to control an Ni-film thickness. Then, with the resistor 8 as one electrode the path 4 is as another electrode to execute an electrolytic plating thereon to reduce the Ni- plated layer 7. The mask is removed, is brushed to remove burrs, a semiconductor element 11 is secured onto the path 4, and is connected to a wire 11. In this configuration no contact resistance occurs at the superimposition of the path 4 and the resistor 8 to improve the heat dissipating efficiency and a hybrid IC durable against large current is thereby obtained.
JP10541879A 1979-08-17 1979-08-17 Manufacture of hybrid integrated circuit Pending JPS5629358A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10541879A JPS5629358A (en) 1979-08-17 1979-08-17 Manufacture of hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10541879A JPS5629358A (en) 1979-08-17 1979-08-17 Manufacture of hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS5629358A true JPS5629358A (en) 1981-03-24

Family

ID=14407046

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10541879A Pending JPS5629358A (en) 1979-08-17 1979-08-17 Manufacture of hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS5629358A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS423717Y1 (en) * 1965-08-05 1967-03-03
JPS5317747A (en) * 1976-08-02 1978-02-18 Sasaki Mooru Kk Natural light inlet tube

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS423717Y1 (en) * 1965-08-05 1967-03-03
JPS5317747A (en) * 1976-08-02 1978-02-18 Sasaki Mooru Kk Natural light inlet tube

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