JPS5915081Y2 - hybrid integrated circuit board - Google Patents
hybrid integrated circuit boardInfo
- Publication number
- JPS5915081Y2 JPS5915081Y2 JP13319078U JP13319078U JPS5915081Y2 JP S5915081 Y2 JPS5915081 Y2 JP S5915081Y2 JP 13319078 U JP13319078 U JP 13319078U JP 13319078 U JP13319078 U JP 13319078U JP S5915081 Y2 JPS5915081 Y2 JP S5915081Y2
- Authority
- JP
- Japan
- Prior art keywords
- nickel
- copper foil
- integrated circuit
- hybrid integrated
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Wire Bonding (AREA)
Description
【考案の詳細な説明】
本考案は、良熱伝導性金属基板からなる混成集積回路基
板に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a hybrid integrated circuit board made of a metal substrate with good thermal conductivity.
近時、良熱伝導性金属基板としてアルミニウム基板表面
に酸化アルミニウムの絶縁膜が形成された混成集積回路
基板が用いられている。Recently, a hybrid integrated circuit board in which an aluminum oxide insulating film is formed on the surface of an aluminum substrate has been used as a metal substrate with good thermal conductivity.
また、酸化アルミニウム膜を施さないアルミニウム基板
をも含む。It also includes an aluminum substrate not coated with an aluminum oxide film.
斯る混成集積回路基板面に銅箔膜が絶縁性接着材層を介
し被着されており、導電路は該銅箔層をエツチングによ
って形成される。A copper foil film is adhered to the surface of the hybrid integrated circuit board via an insulating adhesive layer, and conductive paths are formed by etching the copper foil layer.
混成集積回路基板上に回路を形成するにあたり、銅箔層
で形成された導電路上に半導体素子及びチップ・コンデ
ンサ等の回路素子を接着する製造工程で、多くの熱処理
工程が行われるので、銅箔層の表面が酸化して回路素子
が接着しにくくなる。When forming a circuit on a hybrid integrated circuit board, many heat treatment processes are performed in the manufacturing process of bonding semiconductor elements and circuit elements such as chips and capacitors onto the conductive surface formed by the copper foil layer. The surface of the layer becomes oxidized, making it difficult for circuit elements to adhere.
更に、銅箔層に形成された酸化膜によってボンデングが
困難となる。Furthermore, the oxide film formed on the copper foil layer makes bonding difficult.
そこで、従来銅箔層表面の保護膜としてニッケル箔膜を
形成して熱処理工程で生じる銅箔膜表面層の酸化を防止
するようになされている。Therefore, conventionally, a nickel foil film is formed as a protective film on the surface of the copper foil layer to prevent oxidation of the surface layer of the copper foil film that occurs during the heat treatment process.
更に、混成集積回路基板に大電力用トランジスタを形成
した場合、動作時に導電路が長時間加熱状態となり、導
電路の銅箔層表面を酸化して導電路の破壊をもたらす。Furthermore, when a high-power transistor is formed on a hybrid integrated circuit board, the conductive path is heated for a long time during operation, oxidizing the surface of the copper foil layer of the conductive path and causing destruction of the conductive path.
本考案は、従来の銅箔層の保護膜と比較して優れたニッ
ケル合金鍍金層を提供するにある。The object of the present invention is to provide a nickel alloy plating layer that is superior to the conventional protective film of a copper foil layer.
以下本考案を図面に基づき説明する。The present invention will be explained below based on the drawings.
第１図は、本考案の実施例である混成集積回路基板の断
面図である。FIG. 1 is a sectional view of a hybrid integrated circuit board according to an embodiment of the present invention.
尚、本実施例に於ては、ニッケル・コバルト合金鍍金層
に就いて説明する。In this embodiment, a nickel-cobalt alloy plating layer will be explained.
第１図に於て、１はアルミニウム基板、２は絶縁性の接
着材層、３は銅箔膜、４はニッケル・コバルト合金鍍金
層、５は半導体回路素子、６は金属細線、７は接着材層
である。In Figure 1, 1 is an aluminum substrate, 2 is an insulating adhesive layer, 3 is a copper foil film, 4 is a nickel-cobalt alloy plating layer, 5 is a semiconductor circuit element, 6 is a thin metal wire, and 7 is an adhesive. It is a material layer.
尚、第２図に於て、第１図と同一個所は同一符号が付与
されている。In FIG. 2, the same parts as in FIG. 1 are given the same reference numerals.
８は薄膜抵抗体等の他の回路素子である。8 is another circuit element such as a thin film resistor.
本考案に係る混成集積回路基板に於て、アルミニウム基
板上に貼付した銅箔膜上にニッケル合金鍍金層を形成す
る。In the hybrid integrated circuit board according to the present invention, a nickel alloy plating layer is formed on a copper foil film attached to an aluminum substrate.
以下、ニッケル・コバルト合金鍍金層を被着する電気メ
ツキ法に就いて説明する。The electroplating method for depositing the nickel-cobalt alloy plating layer will be explained below.
ニッケル・コバルト合金鍍金液に銅箔膜を貼付したアル
ミニウム基板を浸漬して、陽極側に純ニツケル板を接続
し、陰極側に金属基板を接続して電界をかけ、金属基板
上の銅箔層表面に約５μ程度の厚さにニッケル・コバル
ト合金鍍金層を被着させる。An aluminum substrate with a copper foil film attached to it is immersed in a nickel-cobalt alloy plating solution, a pure nickel plate is connected to the anode side, a metal substrate is connected to the cathode side, and an electric field is applied to remove the copper foil layer on the metal substrate. A nickel-cobalt alloy plating layer is deposited on the surface to a thickness of approximately 5 μm.
尚、電解メッキによって消費されるコバルト・イオンは
硫酸コバルト液を適宜に合金メッキ液に注入して補う。Incidentally, the cobalt ions consumed by electrolytic plating are supplemented by appropriately injecting a cobalt sulfate solution into the alloy plating solution.
因に、ニッケル・コバルト合金メッキ液は、次のような
組成からなる。Incidentally, the nickel-cobalt alloy plating solution has the following composition.
ＮｉＳＯ４・６Ｈ２０（硫酸ニッケル）・・・・・・６
１．０ｇ、／’ＣＯ３Ｏ４・７Ｈ２０（硫酸コバルト）
・・・・・・２２．０ｇ／ｌＮＨ４Ｃｌ （塩化アンモ
ニウム）・・・・・・２０．８ｇ／ｌＨ２ＳＯ４（硼酸
）・・・・・・１０．４ｇ／７Ｃ７Ｈ４ＮＯ３Ｎａ・２
Ｈ２０（サッカリン・ソーダ）−・・−２，０ｇ／ｌ
斯る溶液の水素イオン濃度（ｐＨ）は、４．０〜５．０
で電解メッキ時のメッキ液の温度は５０〜６０℃が適す
る。NiSO4・6H20 (nickel sulfate)...6
1.0g, /'CO3O4・7H20 (cobalt sulfate)
...22.0g/lNH4Cl (ammonium chloride)...20.8g/lH2SO4 (boric acid)...10.4g/7C7H4NO3Na・2
H20 (saccharin soda)--2,0g/l The hydrogen ion concentration (pH) of such a solution is 4.0-5.0
The temperature of the plating solution during electrolytic plating is preferably 50 to 60°C.
尚、ニッケル・コバルト合金に含有するコバルトの重量
パーセントは、８０％以下が適当である。Note that the weight percent of cobalt contained in the nickel-cobalt alloy is suitably 80% or less.
斯る基板による混成集積回路の形成に就いて説明する。The formation of a hybrid integrated circuit using such a substrate will be explained.
アルミニウム基板１上に被着された銅箔層２上に被着さ
れたニッケル・コバルト合金層４上に半導体素子５、チ
ップ・コンテ゛ンサ、或いは抵抗体８等の回路素子を基
板に接着する場合には、ニッケル・コバルト合金鍍金層
を除去して銅箔層表面を露呈せしめて、回路素子等を半
田等の接着材、或いは熱融着等によって接着する。When bonding a circuit element such as a semiconductor element 5, a chip capacitor, or a resistor 8 to the nickel-cobalt alloy layer 4 which is adhered to the copper foil layer 2 which is adhered to the aluminum substrate 1, to the substrate. In this method, the nickel-cobalt alloy plating layer is removed to expose the surface of the copper foil layer, and circuit elements and the like are bonded using an adhesive such as solder or heat fusion.
周知のように、銅箔層の露呈した状態で加熱すると、銅
箔層表面が酸化され、導電路に金属細線をボンディング
するのが困難となるため、上述のように銅箔層表面にニ
ッケル合金鍍金層からなる保護膜を被覆している。As is well known, if the copper foil layer is heated in an exposed state, the surface of the copper foil layer will oxidize, making it difficult to bond thin metal wires to conductive paths. It is covered with a protective film consisting of a plating layer.
然し乍ら、保護膜には抵抗成分を有するので、保護膜を
除去した後に、回路素子を接着せねばならない。However, since the protective film has a resistance component, the circuit elements must be bonded after removing the protective film.
混成集積回路基板に形成された回路素子を配線するにあ
たっては、保護膜上に直接、金属細線を超音波ボンディ
ング法によって、配線を施して混成集積回路を形成する
。When wiring the circuit elements formed on the hybrid integrated circuit board, wiring is performed directly on the protective film using thin metal wires using an ultrasonic bonding method to form a hybrid integrated circuit.
銅箔面にニッケル・コバルト合金鍍金層を形成すること
によって、混成集積回路の製造工程で多く用いられる熱
処理工程によって、銅箔層表面が酸化されるのを防止で
きると共に、ニッケル・コバルト合金鍍金層は、共析し
て微細結晶の鍍金膜を作る。By forming a nickel-cobalt alloy plating layer on the copper foil surface, it is possible to prevent the surface of the copper foil layer from being oxidized during the heat treatment process often used in the manufacturing process of hybrid integrated circuits. produces a microcrystalline plating film through eutectoid deposition.
従って、従来用いられるニッケル箔膜より一層優れた平
滑面を有し、而もニッケル・コバルト鍍金膜は、合金状
であって強靭であり、且つ防錆力が強い性質を有してい
る。Therefore, the nickel-cobalt plating film has a smoother surface that is superior to the conventionally used nickel foil film, and the nickel-cobalt plating film is alloy-like and strong, and has strong anti-rust properties.
即ち、ニッケル・コバルト合金鍍金層は、銅箔層との密
着度が良く、銅箔層表面に接着されたパワー・トランジ
スタの動作による放熱によって、銅箔層表面が酸化され
るのを防ぐのに効果的である。In other words, the nickel-cobalt alloy plating layer has good adhesion to the copper foil layer, and is effective in preventing the surface of the copper foil layer from being oxidized due to heat dissipation due to the operation of the power transistor bonded to the surface of the copper foil layer. Effective.
更に、ニッケル・コバルト合金鍍金層の表面は、優れた
合金状の平滑面を有するので、金属細線の接着強度が大
であり、混成集積回路基板の形成に極めて有効な保護膜
である。Furthermore, since the surface of the nickel-cobalt alloy plating layer has an excellent alloy-like smooth surface, the adhesion strength of fine metal wires is high, and it is an extremely effective protective film for forming a hybrid integrated circuit board.
本実施例に於ては、ニッケル・コバルト合金鍍金層につ
いて説明したが、他にニッケル・鉄、ニッケル・パラジ
ウム及びニッケル・スズ等のニッケル合金鍍金層も優れ
た混成集積回路基板の保護膜を形成することができる。In this example, a nickel-cobalt alloy plating layer was explained, but other nickel alloy plating layers such as nickel-iron, nickel-palladium, and nickel-tin can also form an excellent protective film for hybrid integrated circuit boards. can do.
斯るニッケル合金層は、ニッケルのみの金属鍍金層と比
較して銅箔層との密着がよく保護膜として種々の効果を
奏するものである。Such a nickel alloy layer has better adhesion to the copper foil layer than a nickel-only metal plating layer, and has various effects as a protective film.
第１図及び第２図は混成集積回路基板の断面図である。
１ニアルミニウム基板、２：絶縁性樹脂、３：銅箔層、
４：ニッケル・コバルト合金鍍金層、５：半導体素子。1 and 2 are cross-sectional views of a hybrid integrated circuit board. 1 aluminum substrate, 2: insulating resin, 3: copper foil layer,
4: Nickel-cobalt alloy plating layer, 5: Semiconductor element.
Claims (1)
を被着して導電路を形成した混成集積回路基板に於て、
該銅箔膜よりなる導電路上にニッケルと他の金属とによ
る合金鍍金層が形成されており、該ニッケルと他の金属
との合金鍍金層にリード線を固着した混成集積回路基板
。In a hybrid integrated circuit board in which a conductive path is formed by depositing a copper foil film on a metal substrate with good thermal conductivity via an insulating adhesive layer,
An alloy plating layer of nickel and another metal is formed on the conductive path made of the copper foil film, and a lead wire is fixed to the alloy plating layer of nickel and the other metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13319078U JPS5915081Y2 (en) | 1978-09-28 | 1978-09-28 | hybrid integrated circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13319078U JPS5915081Y2 (en) | 1978-09-28 | 1978-09-28 | hybrid integrated circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5549545U JPS5549545U (en) | 1980-03-31 |
| JPS5915081Y2 true JPS5915081Y2 (en) | 1984-05-04 |
Family
ID=29101427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13319078U Expired JPS5915081Y2 (en) | 1978-09-28 | 1978-09-28 | hybrid integrated circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5915081Y2 (en) |
-
1978
- 1978-09-28 JP JP13319078U patent/JPS5915081Y2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5549545U (en) | 1980-03-31 |
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