JP4840628B2 - Semiconductor package substrate manufacturing method, semiconductor package manufacturing method using the method, and semiconductor package substrate and semiconductor package using these methods - Google Patents

Semiconductor package substrate manufacturing method, semiconductor package manufacturing method using the method, and semiconductor package substrate and semiconductor package using these methods Download PDF

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JP4840628B2
JP4840628B2 JP2000221615A JP2000221615A JP4840628B2 JP 4840628 B2 JP4840628 B2 JP 4840628B2 JP 2000221615 A JP2000221615 A JP 2000221615A JP 2000221615 A JP2000221615 A JP 2000221615A JP 4840628 B2 JP4840628 B2 JP 4840628B2
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cavity
substrate
copper foil
plating
semiconductor package
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JP2002043454A (en
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正則 中村
匡史 田村
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Showa Denko Materials Co Ltd
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Hitachi Chemical Co Ltd
Showa Denko Materials Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body

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Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a substrate for a semiconductor package that is superior in miniaturization, where, even if an outer layer circuit is also plated using the same kind of material as internal connection terminals to enhance the connections, there is a little variation in the film thickness of plating, and that has a superior wire-bonding property of the internal connection terminals and has a superior connection reliability of outside connection terminals. SOLUTION: A substrate 10 that comprises an opening part to be a cavity at a position for mounting a semiconductor chip and a copper foil 15 is laminated over and adhered to a substrate 20 that comprises at least the internal connection terminals 21 to be connected to the semiconductor chip inside of the cavity, a protective film 13 is formed on the surface of the copper foil, a plating 22 for enhancing the connections is carried out on the surface of the internal connection terminals 21 exposed into the cavity, the protective film 13 on the surface of the copper foil is removed, a hole 30 to be a through hole is opened, a hole inner wall and a cavity inner wall are metallized, unnecessary positions of the copper foil and unnecessary metals are removed by etching, and the internal connection terminals are exposed and the outer layer circuit 26 is formed.

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体パッケージ用基板の製造方法とその方法を用いた半導体パッケージの製造方法及びこれらの方法を用いた半導体パッケージ用基板と半導体パッケージに関する。
【０００２】
【従来の技術】
従来、半導体チップを搭載する箇所に、キャビティを有し、そのキャビティ内に半導体チップと接続する内部接続端子を有する半導体パッケージ用基板の製造方法においては、図４（ａ）に示すように、キャビティとなる開口部を有する基板１１０を、キャビティの内側となる箇所に少なくとも半導体チップと接続する内部接続端子１２１を有する基板１２０の上に重ね、さらにそのキャビティとなる開口部を有する基板１１０の上に、銅箔１０５を貼り合わせた基板であって内部接続端子１２１を保護するための基板１００を重ねて積層接着し、図４（ｂ）に示すように、スルーホールとなる穴１３０をあけ、図４（ｃ）に示すように、穴１３０の内壁を金属化してスルーホール１３１とし、銅箔１０５の不要な箇所をエッチング除去して外層回路１２６を形成した後に、図４（ｄ）に示すように、内部接続端子１２１を保護するための基板１００に、キャビティを形成するための開口部をザグリ加工などで形成し、外層回路１２６の表面にソルダーレジスト１２７を形成し、キャビティ内に露出した内部接続端子１２１の表面に、接続を強化するためのめっき１２２を行うことが知られている。
【０００３】
【発明が解決しようとする課題】
このような半導体パッケージ用基板の製造は、キャビティを形成するための開口部をザグリ加工で形成すると、ザグリ加工のときの加工誤差があるので、その加工誤差分を、図４（ｅ）や図４（ｆ）に示すように、接続端子１２１の面積を広くしたり、外層回路１２６の形成を避けなければならないので、近年の発達に伴う半導体パッケージの小型化にはあまり適していないという課題がある。
【０００４】
更に、外層回路１２６にも内部接続端子１２１と同じ種類の、接続を強化するためのめっき１２２を行うことがあり、その場合には、外層回路１２６とめっき電極との距離と、内部接続端子１２１とめっき電極との距離が異なるため、めっきの膜厚バラツキが大きく、内部接続端子１２１上のめっき厚さは薄く、外層回路１２６上のめっき厚さは厚くなる傾向があり、内部接続端子１２１のワイヤボンディング性が低下し、外層回路１２６の半田接続信頼性が低下するという課題がある。
【０００５】
本発明は、小型化にすぐれ、外層回路にも内部接続端子と同じ種類の、接続を強化するめっきを行う場合でも、めっきの膜厚のばらつきが少なく、内部接続端子のワイヤボンディング性に優れ、かつ外部接続端子の接続信頼性に優れた半導体パッケージ用基板の製造方法とその方法を用いた半導体パッケージの製造方法及びこれらの方法を用いた半導体パッケージ用基板と半導体パッケージを提供することを目的とする。
【０００６】
【課題を解決するための手段】
本発明は以下のことを特徴とする。
（１）半導体チップを搭載する箇所に、キャビティを有し、そのキャビティ内に半導体チップと接続する内部接続端子を有する半導体パッケージ用基板の製造方法において、キャビティとなる開口部を有すると共に銅箔を有する基板を、キャビティの内側となる箇所に少なくとも半導体チップと接続する内部接続端子を有する基板の上に重ねて積層接着し、銅箔の表面に保護膜を形成し、キャビティ内に露出した内部接続端子の表面に接続を強化するためのめっきを行い、銅箔の表面の保護膜を除去し、スルーホールとなる穴をあけ、穴内壁とキャビティ内壁とを金属化し、銅箔の不要な箇所と不要な金属をエッチング除去して、内部接続端子を露出すると共に、他の基板との接続を行なう外部接続端子を有する外層回路を形成し、キャビティ部を保護するようにめっきレジストを形成した後、この外部接続端子の表面に接続を強化するためのめっきをする工程を有する半導体パッケージ用基板の製造方法。
（２）半導体チップを搭載する箇所に、キャビティを有し、そのキャビティ内に半導体チップと接続する内部接続端子を有する半導体パッケージ用基板の製造方法において、キャビティとなる開口部を有する基板を、キャビティの内側となる箇所に少なくとも半導体チップと接続する内部接続端子を有すると共に銅箔を有する基板の上に重ねて積層接着し、銅箔の表面に保護膜を形成し、キャビティ内に露出した内部接続端子の表面に接続を強化するためのめっきを行い、銅箔の表面の保護膜を除去し、スルーホールとなる穴をあけ、穴内壁とキャビティ内壁とを金属化し、銅箔の不要な箇所と不要な金属をエッチング除去して、内部接続端子を露出すると共に、他の基板との接続を行なう外部接続端子を有する外層回路を形成し、キャビティ部を保護するようにめっきレジストを形成した後、この外部接続端子の表面に接続を強化するためのめっきをする工程を有する半導体パッケージ用基板の製造方法。
（３）半導体チップを搭載する箇所に、キャビティを有し、そのキャビティ内に半導体チップと接続する内部接続端子を有する半導体パッケージ用基板の製造方法において、キャビティとなる開口部を有すると共に銅箔を有する基板を、キャビティの内側となる箇所に少なくとも半導体チップと接続する内部接続端子を有すると共に銅箔を有する基板の上に重ねて積層接着し、銅箔の表面に第１の保護膜を形成し、キャビティ内に露出した内部接続端子の表面に接続を強化するためのめっきを行い、銅箔の表面の保護膜を除去し、スルーホールとなる穴をあけ、穴内壁とキャビティ内壁とを金属化し、銅箔の不要な箇所と不要な金属をエッチング除去して、内部接続端子を露出すると共に、他の基板との接続を行なう外部接続端子を有する外層回路を形成し、キャビティ部を保護するようにめっきレジストを形成した後、この外部接続端子の表面に接続を強化するためのめっきをする工程を有する半導体パッケージ用基板の製造方法。
（４）キャビティの内側となる箇所に少なくとも半導体チップと接続する内部接続端子を有する基板が、複数枚であって、下の基板の内部接続端子が露出するように、上の基板に開口部を設ける工程を有する（１）〜（３）のうちいずれかに記載の半導体パッケージ用基板の製造方法。
（５）キャビティの内側となる箇所に少なくとも半導体チップと接続する内部接続端子を有する基板の裏面に、半導体チップの放熱のためのヒートシンクを貼り合わせる工程を有する（１）〜（４）のうちいずれかに記載の半導体パッケージ用基板の製造方法。
（６）基板に開口部を設け、半導体チップを搭載する箇所に直接ヒートシンクが露出するように構成する工程を有する（５）に記載の半導体パッケージ用基板の製造方法。
（７）穴内壁を金属化すると共に、キャビティ内部に露出している内層回路の表面も金属化する（１）〜（６）のうちいずれかに記載の半導体パッケージ用基板の製造方法。
（８）銅箔の不要な箇所をエッチング除去するときに、キャビティ内の不要な金属化部分もエッチング除去する（１）〜（７）のうちいずれかに記載の半導体パッケージ用基板の製造方法。
（９）（１）〜（８）のうちいずれかに記載の方法により製造された半導体パッケージ用基板。
（１０）（１）〜（８）のうちいずれかに記載の方法で製造された半導体パッケージ用基板のキャビティ部に半導体チップを搭載する工程を有する半導体パッケージの製造方法。
（１１）キャビティ内の半導体チップを、封止樹脂で封止する工程を有する（１０）に記載の半導体パッケージの製造方法。
（１２）（１０）または（１１）に記載の方法により製造された半導体パッケージ。
【０００７】
【発明の実施の形態】
本発明によって、半導体チップを搭載する箇所に、キャビティを有し、そのキャビティ内に半導体チップと接続する内部接続端子を有する半導体パッケージ用基板を製造するには、図１（ａ）に示すように、キャビティとなる開口部を有すると共に銅箔１５を有する基板１０を、キャビティの内側となる箇所に少なくとも半導体チップと接続する内部接続端子２１を有する基板２０の上に重ねて積層接着し、図１（ｂ）に示すように、銅箔１５の表面に保護膜１３を形成し、キャビティ内に露出した内部接続端子２１の表面に接続を強化するためのめっき２２を行い、図１（ｃ）に示すように、銅箔１５の表面の保護膜１３を除去し、スルーホール３１となる穴３０をあけ、図１（ｄ）に示すように、穴３０の内壁とキャビティの内壁とを金属化して、スルーホール３１を形成して、図１（ｅ）に示すように、銅箔１５の不要な箇所とキャビティ内の不要な金属とをエッチング除去して、外層回路２６を形成することと、内部接続端子２１の露出とを行うことができる。
この外層回路２６は、上記の説明では、キャビティとなる開口部を有する基板１０に貼り合わされた銅箔１５を加工して形成しているが、銅箔１５は、かならずしもキャビティとなる開口部を有する基板１０の側に貼り合わされていなくてもよく、図３（ａ）に示すように、内部接続端子を有する基板２０に貼り合わされていてもよく、また、図３（ｂ）に示すように、その両方の基板に貼り合わされていてもよい。
また、キャビティの内側となる箇所に少なくとも半導体チップと接続する内部接続端子２１を有する基板２０は、図３（ｃ）に示すように、複数枚であってもよく、その場合には、下の基板２０１の内部接続端子２１が露出するように、上の基板２０２に開口部を設けなければならない。
【０００８】
この半導体パッケージ用基板には、キャビティの内側となる箇所に少なくとも半導体チップと接続する内部接続端子２１を有する基板２０の裏面に、図３（ｄ）に示すように、半導体チップの放熱のためのヒートシンク４１を貼り合わせることができ、さらに、図３（ｅ）に示すように、基板２０に開口部を設け、半導体チップを搭載する箇所に直接ヒートシンク４１が露出するように構成することもできる。このヒートシンク４１の形状は、図３（ｄ）に示すような金属板でもよく、また、図３（ｅ）に示すような突出部を有するものでもよい。
【０００９】
本発明の、キャビティとなる開口部を有すると共に銅箔１５を有する基板１０には、配線板に通常に使用する銅張り積層板を用いることができ、キャビティとなる開口部は、金型による打ち抜き、あるいは、ルータによる加工などによって形成することができる。
【００１０】
キャビティの内側となる箇所に少なくとも半導体チップと接続する内部接続端子２１を有する基板２０には、上記のキャビティとなる開口部を有すると共に銅箔１５を有する基板１０と同様に、配線板に通常に使用する銅張り積層板を用いることができ、内部接続端子２１は、その銅張り積層板の銅箔の上に内部接続端子２１の形状にエッチングレジストを形成して、不要な箇所をエッチング除去して形成することができる。
【００１１】
これらの基板を重ねて積層接着するには、基板の間に、例えば、ガラス布に熱硬化性樹脂を含浸し、加熱・乾燥して、半硬化状にしたプリプレグや、ポリエチレンテレフタレートフィルム上に熱硬化性樹脂を塗布し、加熱・乾燥してドライフィルム状にした、接着シート１６をはさみ、加熱・加圧して積層一体化するなどして行うことができる。
【００１２】
銅箔の表面に形成する保護膜１３には、通常配線板に用いている、めっきレジストと呼ばれる樹脂層を形成することが好ましく、このようなめっきレジストは、エポキシ樹脂のような熱硬化性樹脂を主成分とし、硬化剤、硬化促進剤を含む樹脂組成物を溶剤に混合したインク様のものや、そのような溶液を、ポリエチレンテレフタレートフィルムなどの離型性を有するフィルムの上に塗布し、加熱・乾燥して半硬化状にしたドライフィルム状のものを用いる。インク様の溶液は、スクリーン印刷法によって印刷して必要な形状に保護膜を形成することができる。ドライフィルム状のものは、通常は、硬化剤が光照射によって硬化するものが主流で、被めっき体にラミネートし、形成する形状に光を透過するフォトマスクを重ねて光照射し、露光しなかった部分を現像液で除去することによって保護膜１３を形成することができる。
【００１３】
キャビティ内に露出した内部接続端子２１の表面に接続を強化するためのめっき２２には、ニッケル、金、はんだ、白金、パラジウムなどがあり、ワイヤボンディングなどのためには、ニッケル下地めっきの上に、金、あるいはパラジウム／金のめっきを行うことが好ましい。
このときのニッケル下地めっきの厚さは、１μｍ以上であることが好ましく、これより薄いとニッケルめっきによる硬度が不足し、ワイヤボンディング性が低下する。上限は特にないが、２０μｍを越えるとめっき時間が長くなるがワイヤボンディング性はそれに比例して向上するわけでなく、経済的でない。より好ましくは、５μｍ以上である。
その上に行う金めっきの厚さは、０．１μｍ以上であることが好ましく、これより薄いとボンディングワイヤとの接続強度が不足し、ワイヤボンディング性が低下する。上限は特にないが、２μｍを越えるとめっき時間が長くなるがワイヤボンディング性はそれに比例して向上するわけでなく、経済的でない。より好ましくは、０．５μｍ以上である。さらには、ニッケル下地めっきの上に、パラジウムめっきを行った後に、金めっきを行うとワイヤボンディンブした接続箇所の接続信頼性を高めることができ好ましい。このときのそれぞれのめっきの厚さは、合計で０．１μｍ以上であることが好ましく、より好ましくは０．５μｍ以上である。理由は、金めっきだけの場合と同じであり、上限も、同様に２μｍを越えると経済的でない。
この接続を強化するためのめっき２２は、無電解めっきでも、電解めっきでも行うことができ、このような無電解めっきは、めっきする金属のイオン源と、錯化剤、還元剤、ｐＨ調整剤、安定性を改善する添加剤などから構成されている。めっきに先だって、被めっき体にパラジウムなどのめっき用触媒を付与し、続いて、上記のような無電解めっき液に浸漬することによって行うことができる。さらに、ニッケル下地めっきを行った表面に、金、あるいはパラジウム／金めっきを行うときには、下地めっきのニッケルがめっき用触媒の働きをするので、めっき用触媒を不要する必要はない。電解めっきの場合には、内部接続端子２１と接続された電極用リードを設け、めっきした後の工程で、これを切断する工程を設けなければならない。
【００１４】
銅箔１５の表面に形成した保護膜１３を除去するには、メチルエチルケトンなどのような溶剤に浸漬する方法や、水酸化ナトリウムの水溶液のようなアルカリ性の水溶液をスプレー噴霧して除去することができる。
【００１５】
スルーホール３１となる穴３０をあけるには、ドリルを用い、予め登録した穴径や位置によって、ドリルの直径を選択し、指定された位置までドリルヘッドを移動し、その位置でドリルを回転させながらドリルヘッドを降下させる、数値制御されたドリルマシンで行うことが好ましい。
【００１６】
穴３０の内壁を金属化するには、無電解めっきあるいは、無電解めっきと電解めっきで行うことが好ましく、特に銅めっきが接続抵抗が小さく経済的であることからより好ましい。このような無電解めっきは、めっきする金属のイオン源と、錯化剤、還元剤、ｐＨ調整剤、安定性を改善する添加剤などから構成されている。めっきに先だって、被めっき体にパラジウムなどのめっき用触媒を付与し、続いて、上記のような無電解めっき液に浸漬することによって行うことができる。この無電解めっきは、厚さ１〜２５μｍの範囲で行うことが好ましく、厚さが１μｍ未満であると、わずかのめっき厚さのばらつきで導体抵抗が高くなりやすく好ましくない。この厚さが２５μｍを越えても特性上では特に問題とならないが、無電解めっきそのものが析出速度が低いことから、長時間を要し、経済的でない。厚さを必要とする場合には、無電解めっきで電流が流れる程度に薄く、例えば、０．１〜２μｍ程度に析出させ、その上に電解めっきを用いて行うのが効率的である。この電解めっきには、硫酸浴、ピロリン酸浴、ワット浴など、通常の配線板に用いる電解めっき方法を用いることができる。
【００１７】
この穴３０の内壁を金属化するときに、同時にキャビティ内部に露出している内層回路の表面も金属化され、接続の強化のためのめっき２２の上にも、そのめっき２２を行っていない箇所にも金属が析出される。
【００１８】
銅箔１５の不要な箇所をエッチング除去して外層回路２６を形成するには、上述のめっきレジストと同様の組成物に、エッチング液に対する耐薬品性を向上させる添加剤を用いるか組成物を調整した樹脂組成物の溶液、あるいはドライフィルム状のエッチングレジスト材料を用い、スクリーン印刷やフォト法によってエッチングレジストを形成し、塩化第二銅溶液などのようなエッチング液をスプレー噴霧することにより、エッチングレジストを形成しなかった箇所の銅箔１２を選択的に除去することによって行う。
このときに、上述の接続を強化するためのめっき２２は、エッチング除去のときのストッパーとして働き、内部接続端子２１はエッチング液から保護される。そして、そのめっき２２を電解めっきによって行ったときに用いた、電極用のリードにはめっきされていないので、エッチング除去して、内部接続端子２１を電極用リードから切断することができる。
この銅箔１５の不要な箇所をエッチング除去するときに、キャビティ内の不要な金属化部分もエッチング除去することができ、上述した、穴３０の内壁を金属化するときに、同時にキャビティ内部に露出している内層回路の表面を金属化する工程の後に、上記の工程のエッチングレジストを形成するときに、同様に、キャビティ内に露出した必要とする内層回路の箇所にもエッチングレジストを形成しておき、上記の工程の不要な銅箔１５をエッチング除去するときに、同時に、不要な箇所の内層回路の部分をエッチング除去することができる。このようにして、図１（ｆ）に示すような、放熱を行うための金属層１７も形成することができる。
【００１９】
外層回路２６に、他の基板との接続を行う外部接続端子を形成することができ、その外部接続端子の形状が残るようにエッチングレジストを形成すればよい。
外部接続端子を形成した後に、その表面に接続を強化する金属を形成することもでき、この金属は、内部接続端子１２の表面に行う接続を強化するめっき２２と同様に行うことができる。
このときのニッケル下地めっきの厚さは、１μｍ以上であることが好ましく、これより薄いとニッケルめっきによる硬度が不足し、ワイヤボンディング性が低下する。上限は特にないが、２０μｍを越えるとめっき時間が長くなるがワイヤボンディング性はそれに比例して向上するわけでなく、経済的でない。より好ましくは、５μｍ以上である。
その上に行う金めっきの厚さは、０．１μｍ以上であることが好ましく、これより薄いとはんだボールとの接続強度が不足する。上限は特にないが、２μｍを越えるとめっき時間が長くなるがはんだボールとの接続強度がそれに比例して向上するわけでなく、経済的でない。より好ましくは、０．５μｍ以上である。さらには、ニッケル下地めっきの上に、パラジウムめっきを行った後に、金めっきを行うとはんだボールとの接続信頼性を高めることができ好ましい。このときのそれぞれのめっきの厚さは、合計で０．１μｍ以上であることが好ましく、より好ましくは０．５μｍ以上である。理由は、金めっきだけの場合と同じであり、上限も、同様に２μｍを越えると経済的でない。
【００２０】
また、上記の方法で製造された半導体パッケージ用基板のキャビティ部に半導体チップを搭載すれば、半導体パッケージを製造することができ、さらには、キャビティ内の半導体チップを、封止樹脂で封止することもできる。
【００２１】
【実施例】
図２（ａ）に示すように、両面に１２μｍの銅箔１５ａを貼り合わせた、厚さ０．４ｍｍのガラス布基材エポキシ樹脂銅張り積層板であるＭＣＬ−Ｅ−６７９（日立化成工業株式会社製、商品名）にキャビティとなる開口部３ａを、ルータドリル機であるＮＲ−２Ｃ１８（日立精工業株式会社製、商品名）によりあけ、不要な片面の銅箔１５ａをエッチング除去し、開口部を有する基板１０ａを準備した。
両面に１２μｍの銅箔１５ｂを貼り合わせた、厚さ０．１ｍｍのガラス布基材エポキシ樹脂銅張り積層板であるＭＣＬ−Ｅ−６７９（日立化成工業株式会社製、商品名）にキャビティとなる開口部を、ルータドリル機であるＮＲ−２Ｃ１８（日立精工業株式会社製、商品名）によりあけ、無電解銅めっきを行って両面の銅箔１５ｂを電気的に接続し、開口部の壁に導体を形成し、不要な箇所の銅をエッチング除去して、内層回路２３ｂと内部接続端子２１ｂを有する基板２０ｂを準備した。このときの開口部は、基板１０ａの開口部とほぼ同じ大きさに形成した。また、全ての内部接続端子２１ｂを接続するめっき用リード２４ｂも形成した。
同様にして、両面に１２μｍの銅箔を貼り合わせた、厚さ０．１ｍｍのガラス布基材エポキシ樹脂銅張り積層板であるＭＣＬ−Ｅ−６７９（日立化成工業株式会社製、商品名）にキャビティとなる開口部を、ルータドリル機であるＮＲ−２Ｃ１８（日立精工業株式会社製、商品名）によりあけ、無電解銅めっきを行って両面の銅箔を電気的に接続し、開口部の壁に導体を形成し、不要な箇所の銅をエッチング除去して、内層回路２３ｃと内部接続端子２１ｃを有する基板２０ｃを準備した。このときの開口部は、基板２０ｂの開口部よりも大きく形成した。また、全ての内部接続端子２１ｃを接続するめっき用リード２４ｃも形成した。
同様にして、両面に１２μｍの銅箔１５ｄを貼り合わせた、厚さ０．４ｍｍのガラス布基材エポキシ樹脂銅張り積層板であるＭＣＬ−Ｅ−６７９（日立化成工業株式会社製、商品名）にキャビティとなる開口部を、ルータドリル機であるＮＲ−２Ｃ１８（日立精工業株式会社製、商品名）によりあけ、不要な片面の銅箔１５ｄをエッチング除去し、開口部を有する基板１０ｄを準備した。このときの開口部は、基板２０ｃの開口部より大きく形成した。
接着シートとして、基板１０ａと基板２０ｂの間、及び、基板２０ｃと基板１０ｄの間に挟む接着シート５１ａ，５１ｃには、厚さ２５μｍのエポキシ系ドライフィルム状の接着シートを用い、基板２０ｂと基板２０ｃとの間に挟む接着シート５２ｂには、絶縁性を高めるために、厚さ０．１ｍｍのガラス布基材エポキシ樹脂プリプレグであるＧＥＡ−６７９（日立化成工業株式会社製、商品名）を用いた。そしてこれらの接着シート５１ａ，５１ｃ，５２ｂには、それぞれの基板に設けた開口部に合わせて、開口部を打ち抜き金型で形成した。
これらの材料を、図２（ａ）に示すように重ね、プレス機により、１８０℃の温度で、圧力を３ＭＰａとし、９０分間、加熱・加圧して積層一体化した。
このように積層一体化した多層板のめっきレジスト２８として、図２（ｂ）に示すように、厚さ５０μｍのめっきレジスト用ドライフィルムであるＨ−Ｗ４４０（日立化成工業株式会社製、商品名）をラミネートした後、ザグリ加工で内部接続端子２１ｂ、２１ｃを露出させて、接続を強化するためのめっき２２として、拡大図Ａに示すように、ニッケルめっき２２１と金めっき２２２を続けて行った。このときのニッケルめっき２２１は、ワット浴の無光沢ニッケル浴で、電流密度１．３Ａ／ｄｍ2、金めっき２２２は、テンテレックス４０１液（日本ＥＥＪＡ社製、商品名）、０．４Ａ／ｄｍ2の条件で行った。このときのニッケルめっき２２１の厚さは２μｍ、金めっき２２２の厚さは０．１μｍであった。
図２（ｃ）に示すように、前記ドライフィルムのめっきレジストを、メチルエチルケトンに浸漬して剥離除去した後、所定の場所にＮＣドリル機により、スルーホール３１となる穴をあけ、無電解銅めっき液であるＬ５９（日立化成工業株式会社製、商品名）に浸漬し、厚さ２５μｍに銅５３を析出させた。
更に、その銅５３の表面に、外層回路２６の形状にエッチングレジストを形成し、エッチング液としてアルカリ系エッチング液を用いて、エッチングレジストから露出した銅５３をエッチング除去して、外層回路２６を形成した。このときに、キャビティの内側にはエッチングレジストを形成しなかったので、内部接続端子２１ｂ、２１ｃが露出し、めっきリード２４ｂ、２４ｃはエッチング除去された。その後、ソルダーレジスト用ドライフィルムであるＳＲ−７０００（日立化成工業株式会社製、商品名）をラミネートし、図２（ｄ）に示すように、外部接続端子の箇所を除いてソルダーレジスト２７を形成し、更に、めっきレジスト用ドライフィルムであるＨ−Ｋ６５０（日立化成工業株式会社製、商品名）をラミネートし、キャビティ部を保護するように、めっきレジスト２８を形成し、外部接続端子に、接続を強化するためのめっき２２として、ニッケルめっきと金めっきを続けて行った。このときのニッケルめっきは、ワット浴の無光沢ニッケル浴で、電流密度１．３Ａ／ｄｍ2、金めっきは、テンテレックス４０１液（日本ＥＥＪＡ社製、商品名）、０．４Ａ／ｄｍ2であった。このときのニッケルめっきの厚さは２μｍ、金めっきの厚さは０．１μｍであった。
その後、ヒートシンク４１を接着し、外形加工により所定のサイズに個片加工した。
次に、図２（ｅ）に示すように、裏面にダイボンディングフィルムを貼り合わせた半導体チップ６を、ヒートシンク４１の上に接着・固定し、半導体チップ６の端子と内部接続端子２１をボンディングワイヤ７で接続した後、封止樹脂８で封止した。
【００２２】
本実施例の効果として、最外層の基板を窓加工して積層した事により、キャビティ部の蓋を加工しキャビティを露出させないようにした事により、加工位置精度が向上した。
更に、キャビティ部の先にニッケル金めっきを行い、永久ソルダーレジスト形成後外層パッド部のニッケル金めっきを行うことにより、金めっき厚さがキャビティ部を厚く、外層パッド部を薄く設定することができる事によい、外部接続の信頼性が向上することができた。
【００２３】
【発明の効果】
以上に説明したとおり、本発明によって、小型化にすぐれ、外層回路にも内部接続端子と同じ種類の、接続を強化するめっきを行う場合でも、めっきの膜厚のばらつきが少なく、内部接続端子のワイヤボンディング性に優れ、かつ外部接続端子の接続信頼性に優れた半導体パッケージ用基板の製造方法とその方法を用いた半導体パッケージの製造方法及びこれらの方法を用いた半導体パッケージ用基板と半導体パッケージを提供することができた。
【図面の簡単な説明】
【図１】（ａ）〜（ｄ）は、それぞれ、本発明の原理を説明するための各工程での断面図であり、（ｅ）は、その実施態様の一例を示す断面図である。
【図２】（ａ）〜（ｋ）は、それぞれ本発明の一実施例を示す、各工程における断面図である。
【図３】（ａ）〜（ｅ）は、それぞれ、本発明の他の態様を示す断面図である。
【図４】（ａ）〜（ｆ）は、それぞれ、従来例を示す、各工程での断面図である。
【符号の説明】
６．半導体チップ
７．ボンディングワイヤ
８．封止樹脂
１０，１０ａ，１０ｄ，１１０．開口部を有する基板
１３．保護膜
１５，１５ａ，１５ｄ．銅箔
１６．放熱を行うための金属層
１２０，２０，２０ｂ，２０ｃ．内部接続端子を有する基板
２１，２１ｂ，２１ｃ．内部接続端子
２２．接続を強化するためのめっき
２３ｂ，２３ｃ．内層回路
２４ｂ，２４ｃ．めっき用リード
２６．外層回路
２７．ソルダーレジスト
２８．めっきレジスト
２９．外部接続端子
３０，１３０．スルーホール
３１，１３１．スルーホールとなる穴
４１．ヒートシンク
１００．内部接続端子を保護するための基板
２０１．下の基板
２０２．上の基板
１３１．スルーホール
１２６．外層回路
１２２．接続を強化するためのめっき[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor package substrate, a method for manufacturing a semiconductor package using the method, and a semiconductor package substrate and a semiconductor package using these methods.
[0002]
[Prior art]
Conventionally, in a method for manufacturing a substrate for a semiconductor package having a cavity at a place where a semiconductor chip is mounted and having an internal connection terminal connected to the semiconductor chip in the cavity, as shown in FIG. A substrate 110 having an opening to be formed is overlaid on a substrate 120 having an internal connection terminal 121 connected to at least a semiconductor chip at a position inside the cavity, and further on the substrate 110 having an opening to be the cavity. Then, the substrate 100 on which the copper foil 105 is bonded and the substrate 100 for protecting the internal connection terminals 121 are stacked and bonded together, and as shown in FIG. 4 (c), the inner wall of the hole 130 is metalized to form a through hole 131, and unnecessary portions of the copper foil 105 are removed by etching. After forming the layer circuit 126, as shown in FIG. 4D, an opening for forming a cavity is formed in the substrate 100 for protecting the internal connection terminals 121 by counterboring or the like, and the outer layer circuit 126 is formed. It is known that a solder resist 127 is formed on the surface of the internal connection terminal 121, and plating 122 for reinforcing the connection is performed on the surface of the internal connection terminal 121 exposed in the cavity.
[0003]
[Problems to be solved by the invention]
In manufacturing such a substrate for a semiconductor package, if an opening for forming a cavity is formed by counterboring, there is a processing error at the time of counterboring. Therefore, the processing error is shown in FIG. As shown in FIG. 4 (f), since the area of the connection terminal 121 must be increased and the formation of the outer layer circuit 126 must be avoided, there is a problem that it is not suitable for miniaturization of a semiconductor package accompanying recent development. is there.
[0004]
Further, the outer layer circuit 126 may be subjected to the same type of plating 122 as that of the internal connection terminal 121 to reinforce the connection. In this case, the distance between the outer layer circuit 126 and the plating electrode, the internal connection terminal 121 and the like. Since the distance between the electrode and the plating electrode is different, the film thickness variation of the plating is large, the plating thickness on the internal connection terminal 121 is thin, and the plating thickness on the outer layer circuit 126 tends to be thick. There is a problem that the wire bonding property is lowered and the solder connection reliability of the outer layer circuit 126 is lowered.
[0005]
The present invention is excellent in miniaturization, the outer layer circuit is the same type as the internal connection terminal, even when plating for reinforcing the connection is performed, there is little variation in the film thickness of the plating, and the wire bonding property of the internal connection terminal is excellent. An object of the present invention is to provide a semiconductor package substrate manufacturing method excellent in connection reliability of external connection terminals, a semiconductor package manufacturing method using the method, and a semiconductor package substrate and semiconductor package using these methods. To do.
[0006]
[Means for Solving the Problems]
The present invention is characterized by the following.
(1) In a method for manufacturing a substrate for a semiconductor package having a cavity at a place where a semiconductor chip is mounted and having an internal connection terminal connected to the semiconductor chip in the cavity, an opening serving as a cavity and a copper foil The substrate that has the internal connection terminal that is connected to the semiconductor chip at least at the location inside the cavity is stacked and bonded, and a protective film is formed on the surface of the copper foil, and the internal connection exposed in the cavity Plating to strengthen the connection on the surface of the terminal, removing the protective film on the surface of the copper foil, drilling a hole to be a through hole, metallizing the inner wall of the hole and the inner wall of the cavity, Unnecessary metal is removed by etching to expose the internal connection terminals and to form an outer layer circuit having external connection terminals for connection to other substrates. After forming the plating resist to protect the parts, a method of manufacturing a semiconductor package substrate, comprising the step of plating to strengthen the connection to the surface of the external connection terminal.
(2) In a method for manufacturing a substrate for a semiconductor package having a cavity at a place where a semiconductor chip is mounted and having an internal connection terminal connected to the semiconductor chip in the cavity, a substrate having an opening serving as a cavity is Have internal connection terminals that connect at least to the semiconductor chip at the inside of the substrate, and are stacked and bonded on a substrate having a copper foil to form a protective film on the surface of the copper foil, and the internal connection exposed in the cavity Plating to strengthen the connection on the surface of the terminal, removing the protective film on the surface of the copper foil, drilling a hole to be a through hole, metallizing the inner wall of the hole and the inner wall of the cavity, Unnecessary metal is removed by etching to expose the internal connection terminals and to form an outer layer circuit having external connection terminals for connection to other substrates. After forming the plating resist to protect the parts, a method of manufacturing a semiconductor package substrate, comprising the step of plating to strengthen the connection to the surface of the external connection terminal.
(3) In a method for manufacturing a substrate for a semiconductor package having a cavity at a location where a semiconductor chip is mounted and having an internal connection terminal connected to the semiconductor chip in the cavity, an opening serving as a cavity and a copper foil A first protective film is formed on the surface of the copper foil by stacking and adhering the substrate having at least an internal connection terminal connected to the semiconductor chip on the inside of the cavity and overlapping the copper foil on the substrate; , Plating to reinforce the connection on the surface of the internal connection terminal exposed in the cavity, removing the protective film on the surface of the copper foil, drilling a hole to become a through hole, metallizing the inner wall of the hole and the inner wall of the cavity Etching away unnecessary portions of copper foil and unnecessary metal to expose internal connection terminals and external connection terminals to connect to other substrates Forming a circuit, after forming the plating resist to protect the cavity, a method of manufacturing a semiconductor package substrate, comprising the step of plating to strengthen the connection to the surface of the external connection terminal.
(4) There are a plurality of substrates having internal connection terminals connected to at least a semiconductor chip at a location inside the cavity, and an opening is formed in the upper substrate so that the internal connection terminals of the lower substrate are exposed. (1)-(3) which has the process to provide One of The manufacturing method of the board | substrate for semiconductor packages of description.
(5) The method includes a step of attaching a heat sink for heat dissipation of the semiconductor chip to the back surface of the substrate having at least an internal connection terminal connected to the semiconductor chip at a location inside the cavity. Any one of (1) to (4) A method for manufacturing a semiconductor package substrate according to claim 1.
(6) The method for manufacturing a substrate for a semiconductor package according to (5), further comprising a step of providing an opening in the substrate so that the heat sink is directly exposed at a position where the semiconductor chip is mounted.
(7) The method for manufacturing a substrate for a semiconductor package according to any one of (1) to (6), wherein the inner wall of the hole is metallized and the surface of the inner layer circuit exposed inside the cavity is also metallized.
(8) The method for manufacturing a semiconductor package substrate according to any one of (1) to (7), wherein when unnecessary portions of the copper foil are removed by etching, unnecessary metallized portions in the cavities are also removed by etching.
(9) A substrate for a semiconductor package manufactured by the method according to any one of (1) to (8).
(10) A method for manufacturing a semiconductor package, including a step of mounting a semiconductor chip in a cavity portion of a semiconductor package substrate manufactured by the method according to any one of (1) to (8).
(11) The method for manufacturing a semiconductor package according to (10), including a step of sealing the semiconductor chip in the cavity with a sealing resin.
(12) A semiconductor package manufactured by the method according to (10) or (11).
[0007]
DETAILED DESCRIPTION OF THE INVENTION
According to the present invention, in order to manufacture a semiconductor package substrate having a cavity at a place where a semiconductor chip is mounted and having an internal connection terminal connected to the semiconductor chip in the cavity, as shown in FIG. A substrate 10 having an opening serving as a cavity and having a copper foil 15 is laminated and adhered on a substrate 20 having an internal connection terminal 21 connected to at least a semiconductor chip at a location inside the cavity. As shown in FIG. 1B, a protective film 13 is formed on the surface of the copper foil 15, and plating 22 for reinforcing the connection is performed on the surface of the internal connection terminal 21 exposed in the cavity. As shown in the figure, the protective film 13 on the surface of the copper foil 15 is removed, a hole 30 to be a through hole 31 is formed, and the inner wall of the hole 30 and the inner wall of the cavity are made of gold as shown in FIG. And forming a through hole 31 and forming an outer layer circuit 26 by etching away unnecessary portions of the copper foil 15 and unnecessary metal in the cavity, as shown in FIG. The internal connection terminal 21 can be exposed.
In the above description, the outer layer circuit 26 is formed by processing the copper foil 15 bonded to the substrate 10 having an opening serving as a cavity. However, the copper foil 15 has an opening serving as a cavity. It may not be bonded to the substrate 10 side, and may be bonded to the substrate 20 having the internal connection terminals as shown in FIG. 3 (a). Also, as shown in FIG. 3 (b), You may affix on both the board | substrates.
In addition, as shown in FIG. 3C, the substrate 20 having the internal connection terminals 21 that are connected to at least the semiconductor chip at the location inside the cavity may be a plurality of substrates. An opening must be provided in the upper substrate 202 so that the internal connection terminals 21 of the substrate 201 are exposed.
[0008]
In this semiconductor package substrate, as shown in FIG. 3D, on the back surface of the substrate 20 having an internal connection terminal 21 connected to at least the semiconductor chip at a location inside the cavity, The heat sink 41 can be bonded together, and as shown in FIG. 3E, an opening can be provided in the substrate 20, and the heat sink 41 can be directly exposed at the location where the semiconductor chip is mounted. The shape of the heat sink 41 may be a metal plate as shown in FIG. 3D, or may have a protrusion as shown in FIG.
[0009]
For the substrate 10 having an opening serving as a cavity and the copper foil 15 of the present invention, a copper-clad laminate usually used for a wiring board can be used, and the opening serving as a cavity is punched by a mold. Alternatively, it can be formed by processing with a router.
[0010]
The substrate 20 having the internal connection terminals 21 connected to at least the semiconductor chip at the inside of the cavity has the opening serving as the cavity and has the copper foil 15 as well as the wiring board. The copper-clad laminate to be used can be used, and the internal connection terminal 21 is formed by forming an etching resist in the shape of the internal connection terminal 21 on the copper foil of the copper-clad laminate and etching away unnecessary portions. Can be formed.
[0011]
In order to laminate and adhere these substrates, for example, a glass cloth is impregnated with a thermosetting resin, heated and dried, and heated on a semi-cured prepreg or polyethylene terephthalate film. It can be performed by applying a curable resin, heating and drying to form a dry film, sandwiching the adhesive sheet 16, heating and pressurizing, and laminating and integrating.
[0012]
The protective film 13 formed on the surface of the copper foil is preferably formed with a resin layer called a plating resist, which is usually used for a wiring board. Such a plating resist is a thermosetting resin such as an epoxy resin. The ink-like thing which mixed the resin composition containing a hardening | curing agent and a hardening accelerator with a solvent as a main component, and such a solution are apply | coated on the film which has mold release properties, such as a polyethylene terephthalate film, Use a dry film that is semi-cured by heating and drying. The ink-like solution can be printed by a screen printing method to form a protective film in a required shape. The dry film type is usually a curing agent that cures by light irradiation, and is laminated to the object to be plated, and a photomask that transmits light is superimposed on the shape to be formed. The protective film 13 can be formed by removing the portion with a developer.
[0013]
The plating 22 for reinforcing the connection on the surface of the internal connection terminal 21 exposed in the cavity includes nickel, gold, solder, platinum, palladium, and the like. It is preferable to perform gold plating or palladium / gold plating.
At this time, the thickness of the nickel base plating is preferably 1 μm or more, and if it is thinner than this, the hardness due to nickel plating is insufficient and the wire bonding property is lowered. There is no particular upper limit, but if it exceeds 20 μm, the plating time becomes longer, but the wire bonding property is not improved proportionally and is not economical. More preferably, it is 5 μm or more.
The thickness of the gold plating performed thereon is preferably 0.1 μm or more, and if it is thinner than this, the connection strength with the bonding wire is insufficient and the wire bonding property is deteriorated. There is no particular upper limit, but if it exceeds 2 μm, the plating time becomes longer, but the wire bonding property is not improved proportionally and is not economical. More preferably, it is 0.5 μm or more. Furthermore, it is preferable to perform gold plating after performing palladium plating on the nickel base plating, since the connection reliability of the wire-bonded connection portion can be improved. The total thickness of each plating at this time is preferably 0.1 μm or more, and more preferably 0.5 μm or more. The reason is the same as in the case of only gold plating, and the upper limit is also not economical if it exceeds 2 μm.
The plating 22 for strengthening the connection can be performed by electroless plating or electrolytic plating. Such electroless plating includes an ion source of a metal to be plated, a complexing agent, a reducing agent, and a pH adjusting agent. It consists of additives that improve stability. Prior to plating, a plating catalyst such as palladium can be applied to the object to be plated, and then immersed in the electroless plating solution as described above. Further, when gold or palladium / gold plating is performed on the surface on which the nickel base plating has been performed, since the nickel of the base plating functions as a plating catalyst, it is not necessary to use a plating catalyst. In the case of electrolytic plating, an electrode lead connected to the internal connection terminal 21 is provided, and a step of cutting the electrode lead must be provided in the step after plating.
[0014]
In order to remove the protective film 13 formed on the surface of the copper foil 15, a method of immersing in a solvent such as methyl ethyl ketone, or an alkaline aqueous solution such as an aqueous solution of sodium hydroxide can be removed by spraying. .
[0015]
To drill the hole 30 to be the through hole 31, use a drill, select the diameter of the drill according to the hole diameter and position registered in advance, move the drill head to the specified position, and rotate the drill at that position. It is preferable to use a numerically controlled drill machine that lowers the drill head.
[0016]
In order to metallize the inner wall of the hole 30, electroless plating or electroless plating and electrolytic plating are preferably performed, and copper plating is more preferable because it has a low connection resistance and is economical. Such electroless plating includes an ion source of metal to be plated, a complexing agent, a reducing agent, a pH adjusting agent, an additive for improving stability, and the like. Prior to plating, a plating catalyst such as palladium can be applied to the object to be plated, and then immersed in the electroless plating solution as described above. This electroless plating is preferably performed in a thickness range of 1 to 25 μm. If the thickness is less than 1 μm, the conductor resistance tends to be high due to slight variations in plating thickness, which is not preferable. Even if the thickness exceeds 25 μm, there is no particular problem in terms of characteristics. However, since the electroless plating itself has a low deposition rate, it takes a long time and is not economical. When the thickness is required, it is efficient that the electroless plating is thin enough to allow current to flow, for example, is deposited on the order of 0.1 to 2 μm, and electrolytic plating is performed thereon. For this electrolytic plating, an electrolytic plating method used for a normal wiring board, such as a sulfuric acid bath, a pyrophosphoric acid bath, or a watt bath, can be used.
[0017]
When the inner wall of the hole 30 is metalized, the surface of the inner layer circuit exposed to the inside of the cavity is also metalized, and the plating 22 is not applied on the plating 22 for strengthening the connection. Also metal is deposited.
[0018]
In order to form the outer layer circuit 26 by removing unnecessary portions of the copper foil 15 by etching, an additive for improving chemical resistance against the etching solution is used in the same composition as the plating resist described above or the composition is adjusted. The etching resist is formed by spraying an etching solution such as a cupric chloride solution using a resin composition solution or a dry film etching resist material, and forming an etching resist by screen printing or photolithography. This is carried out by selectively removing the copper foil 12 at the place where the film is not formed.
At this time, the above-described plating 22 for strengthening the connection functions as a stopper at the time of etching removal, and the internal connection terminal 21 is protected from the etching solution. Since the electrode lead used when the plating 22 is performed by electrolytic plating is not plated, the internal connection terminal 21 can be cut from the electrode lead by etching away.
When unnecessary portions of the copper foil 15 are removed by etching, unnecessary metallized portions in the cavity can also be removed by etching. When the inner wall of the hole 30 described above is metalized, it is exposed to the inside of the cavity at the same time. After the step of metallizing the surface of the inner layer circuit, when forming the etching resist in the above step, similarly, the etching resist is also formed on the portion of the inner layer circuit that is required to be exposed in the cavity. In addition, when the unnecessary copper foil 15 in the above process is removed by etching, an unnecessary portion of the inner layer circuit can be simultaneously removed by etching. In this way, a metal layer 17 for heat dissipation as shown in FIG. 1 (f) can also be formed.
[0019]
An external connection terminal for connecting to another substrate can be formed in the outer layer circuit 26, and an etching resist may be formed so that the shape of the external connection terminal remains.
After the external connection terminal is formed, a metal that reinforces the connection can be formed on the surface, and this metal can be formed in the same manner as the plating 22 that reinforces the connection to be made on the surface of the internal connection terminal 12.
At this time, the thickness of the nickel base plating is preferably 1 μm or more, and if it is thinner than this, the hardness due to nickel plating is insufficient and the wire bonding property is lowered. There is no particular upper limit, but if it exceeds 20 μm, the plating time becomes longer, but the wire bonding property is not improved proportionally and is not economical. More preferably, it is 5 μm or more.
The thickness of the gold plating performed thereon is preferably 0.1 μm or more, and if it is thinner than this, the connection strength with the solder ball is insufficient. Although there is no particular upper limit, if it exceeds 2 μm, the plating time becomes longer, but the connection strength with the solder ball does not improve in proportion thereto, and is not economical. More preferably, it is 0.5 μm or more. Furthermore, it is preferable to perform gold plating after performing palladium plating on the nickel base plating because the connection reliability with the solder balls can be improved. The total thickness of each plating at this time is preferably 0.1 μm or more, and more preferably 0.5 μm or more. The reason is the same as in the case of only gold plating, and the upper limit is also not economical if it exceeds 2 μm.
[0020]
Further, if a semiconductor chip is mounted on the cavity portion of the semiconductor package substrate manufactured by the above method, the semiconductor package can be manufactured, and further, the semiconductor chip in the cavity is sealed with a sealing resin. You can also
[0021]
【Example】
As shown in FIG. 2 (a), MCL-E-679 (Hitachi Chemical Co., Ltd.), which is a 0.4 mm thick glass cloth base epoxy resin copper clad laminate with 12 μm copper foil 15a bonded to both sides. Open the opening 3a which becomes a cavity in the company-made product name) with NR-2C18 (trade name, manufactured by Hitachi Seiko Co., Ltd.) which is a router drill machine, and remove the unnecessary copper foil 15a on one side by etching. A substrate 10a having a portion was prepared.
MCL-E-679 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a 0.1 mm thick glass cloth base epoxy resin copper-clad laminate with 12 μm copper foil 15b bonded to both sides, becomes a cavity. Open the opening with NR-2C18 (trade name, manufactured by Hitachi Seiko Co., Ltd.) which is a router drill machine, and perform electroless copper plating to electrically connect the copper foils 15b on both sides to the wall of the opening. A conductor was formed, and unnecessary portions of copper were removed by etching to prepare a substrate 20b having an inner layer circuit 23b and an internal connection terminal 21b. The opening at this time was formed to have almost the same size as the opening of the substrate 10a. Moreover, the lead 24b for plating which connects all the internal connection terminals 21b was also formed.
In the same manner, MCL-E-679 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a 0.1 mm thick glass cloth base epoxy resin copper clad laminate with 12 μm copper foil bonded to both sides. Open the opening that becomes the cavity with NR-2C18 (trade name, manufactured by Hitachi Seiko Co., Ltd.), which is a router drill machine, and perform electroless copper plating to electrically connect the copper foils on both sides. A conductor was formed on the wall, and unnecessary portions of copper were removed by etching to prepare a substrate 20c having an inner layer circuit 23c and an internal connection terminal 21c. The opening at this time was formed larger than the opening of the substrate 20b. Also, plating leads 24c that connect all the internal connection terminals 21c were formed.
Similarly, MCL-E-679 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a 0.4 mm thick glass cloth base epoxy resin copper-clad laminate with 12 μm copper foil 15d bonded to both sides. An opening which becomes a cavity is opened by NR-2C18 (trade name, manufactured by Hitachi Seiko Co., Ltd.) which is a router drill machine, and unnecessary copper foil 15d is removed by etching to prepare a substrate 10d having an opening. did. The opening at this time was formed larger than the opening of the substrate 20c.
As adhesive sheets, adhesive sheets 51a and 51c sandwiched between the substrate 10a and the substrate 20b and between the substrate 20c and the substrate 10d are epoxy-type dry film adhesive sheets having a thickness of 25 μm, and the substrate 20b and the substrate GEA-679 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a glass cloth base epoxy resin prepreg having a thickness of 0.1 mm, is used for the adhesive sheet 52b sandwiched between 20c and 20c. It was. And in these adhesive sheets 51a, 51c, 52b, openings were formed by punching dies in accordance with the openings provided in the respective substrates.
These materials were stacked as shown in FIG. 2 (a), and were laminated and integrated by heating and pressurizing for 90 minutes at a temperature of 180 ° C. and a pressure of 3 MPa using a press.
As shown in FIG. 2B, H-W440 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a dry film for a plating resist having a thickness of 50 μm, is used as the plating resist 28 of the multilayer board thus laminated and integrated. Then, as shown in the enlarged view A, nickel plating 221 and gold plating 222 were continuously performed as plating 22 for exposing the internal connection terminals 21b and 21c by counterboring and strengthening the connection. At this time, the nickel plating 221 is a matte nickel bath of a watt bath and has a current density of 1.3 A / dm. 2 , Gold plating 222 is Tentelex 401 liquid (trade name, manufactured by Japan EEJA), 0.4 A / dm 2 It went on condition of. At this time, the nickel plating 221 had a thickness of 2 μm, and the gold plating 222 had a thickness of 0.1 μm.
As shown in FIG. 2 (c), after the plating resist of the dry film was immersed and removed in methyl ethyl ketone, a hole to be a through hole 31 was made in a predetermined place by an NC drill machine, and electroless copper plating was performed. It was immersed in a liquid L59 (trade name, manufactured by Hitachi Chemical Co., Ltd.), and copper 53 was deposited to a thickness of 25 μm.
Further, an etching resist is formed in the shape of the outer layer circuit 26 on the surface of the copper 53, and the outer layer circuit 26 is formed by etching away the copper 53 exposed from the etching resist using an alkaline etching solution as an etching solution. did. At this time, since no etching resist was formed inside the cavity, the internal connection terminals 21b and 21c were exposed, and the plating leads 24b and 24c were removed by etching. Thereafter, SR-7000 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a solder resist dry film, is laminated, and as shown in FIG. 2 (d), the solder resist 27 is formed except for the locations of the external connection terminals. Furthermore, H-K650 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a dry film for plating resist, is laminated, plating resist 28 is formed so as to protect the cavity portion, and the external connection terminal is connected. As plating 22 for strengthening, nickel plating and gold plating were continuously performed. The nickel plating at this time is a matte nickel bath of Watt bath, and a current density of 1.3 A / dm. 2 Gold plating is Tentelex 401 liquid (trade name, manufactured by Japan EEJA), 0.4 A / dm 2 Met. At this time, the thickness of the nickel plating was 2 μm, and the thickness of the gold plating was 0.1 μm.
Thereafter, the heat sink 41 was bonded, and individual pieces were processed into a predetermined size by external processing.
Next, as shown in FIG. 2 (e), the semiconductor chip 6 with the die bonding film bonded to the back surface is bonded and fixed on the heat sink 41, and the terminals of the semiconductor chip 6 and the internal connection terminals 21 are bonded to the bonding wires. After the connection at 7, the resin was sealed with a sealing resin 8.
[0022]
As an effect of the present embodiment, the processing position accuracy was improved by processing the lid of the cavity portion so as not to expose the cavity by processing the outermost substrate by laminating and laminating.
Furthermore, by performing nickel gold plating on the tip of the cavity portion and performing nickel gold plating on the outer layer pad portion after the permanent solder resist is formed, the gold plating thickness can be set thicker and the outer layer pad portion thinner. Good thing, the reliability of external connection was improved.
[0023]
【The invention's effect】
As described above, according to the present invention, the present invention is excellent in miniaturization, and even when the outer layer circuit is subjected to the same kind of plating as that of the internal connection terminal, the film thickness variation of the plating is small. Semiconductor package substrate manufacturing method excellent in wire bonding property and excellent connection reliability of external connection terminals, semiconductor package manufacturing method using the method, and semiconductor package substrate and semiconductor package using these methods Could be provided.
[Brief description of the drawings]
FIGS. 1A to 1D are cross-sectional views at respective steps for explaining the principle of the present invention, and FIG. 1E is a cross-sectional view showing an example of the embodiment.
FIGS. 2A to 2K are cross-sectional views in respective steps, showing an embodiment of the present invention.
FIGS. 3A to 3E are cross-sectional views showing other embodiments of the present invention, respectively.
4 (a) to 4 (f) are cross-sectional views at respective steps showing a conventional example.
[Explanation of symbols]
6). Semiconductor chip
7). Bonding wire
8). Sealing resin
10, 10a, 10d, 110. Substrate with opening
13. Protective film
15, 15a, 15d. Copper foil
16. Metal layer for heat dissipation
120, 20, 20b, 20c. Board with internal connection terminals
21, 21b, 21c. Internal connection terminal
22. Plating to strengthen connections
23b, 23c. Inner layer circuit
24b, 24c. Lead for plating
26. Outer layer circuit
27. Solder resist
28. Plating resist
29. External connection terminal
30, 130. Through hole
31, 131. Hole to be a through hole
41. heatsink
100. Board to protect internal connection terminals
201. Lower board
202. Top board
131. Through hole
126. Outer layer circuit
122. Plating to strengthen connections

Claims (12)

半導体チップを搭載する箇所に、キャビティを有し、そのキャビティ内に半導体チップと接続する内部接続端子を有する半導体パッケージ用基板の製造方法において、キャビティとなる開口部を有すると共に銅箔を有する基板を、キャビティの内側となる箇所に少なくとも半導体チップと接続する内部接続端子を有する基板の上に重ねて積層接着し、銅箔の表面に保護膜を形成し、キャビティ内に露出した内部接続端子の表面に接続を強化するためのめっきを行い、銅箔の表面の保護膜を除去し、スルーホールとなる穴をあけ、穴内壁とキャビティ内壁とを金属化し、銅箔の不要な箇所と不要な金属をエッチング除去して、内部接続端子を露出すると共に、他の基板との接続を行なう外部接続端子を有する外層回路を形成し、キャビティ部を保護するようにめっきレジストを形成した後、この外部接続端子の表面に接続を強化するためのめっきをする工程を有する半導体パッケージ用基板の製造方法。  In a method for manufacturing a substrate for a semiconductor package having a cavity at a location where a semiconductor chip is mounted and having an internal connection terminal connected to the semiconductor chip in the cavity, a substrate having an opening serving as a cavity and having a copper foil is provided. The surface of the internal connection terminal exposed in the cavity is formed by stacking and adhering on the substrate having at least the internal connection terminal connected to the semiconductor chip at a position inside the cavity, and forming a protective film on the surface of the copper foil. Plating to strengthen the connection to the copper foil, removing the protective film on the surface of the copper foil, drilling a hole to become a through hole, metallizing the inner wall of the hole and the inner wall of the cavity, unnecessary portions of the copper foil and unnecessary metal Etching is performed to expose the internal connection terminals and form an outer layer circuit having external connection terminals for connection to other substrates. After forming the plating resist to protect, a method of manufacturing a semiconductor package substrate, comprising the step of plating to strengthen the connection to the surface of the external connection terminal. 半導体チップを搭載する箇所に、キャビティを有し、そのキャビティ内に半導体チップと接続する内部接続端子を有する半導体パッケージ用基板の製造方法において、キャビティとなる開口部を有する基板を、キャビティの内側となる箇所に少なくとも半導体チップと接続する内部接続端子を有すると共に銅箔を有する基板の上に重ねて積層接着し、銅箔の表面に保護膜を形成し、キャビティ内に露出した内部接続端子の表面に接続を強化するためのめっきを行い、銅箔の表面の保護膜を除去し、スルーホールとなる穴をあけ、穴内壁とキャビティ内壁とを金属化し、銅箔の不要な箇所と不要な金属をエッチング除去して、内部接続端子を露出すると共に、他の基板との接続を行なう外部接続端子を有する外層回路を形成し、キャビティ部を保護するようにめっきレジストを形成した後、この外部接続端子の表面に接続を強化するためのめっきをする工程を有する半導体パッケージ用基板の製造方法。  In a method for manufacturing a substrate for a semiconductor package having a cavity at a position where a semiconductor chip is mounted and having an internal connection terminal connected to the semiconductor chip in the cavity, the substrate having an opening serving as a cavity is defined as an inside of the cavity. The internal connection terminal connected to the semiconductor chip at least in a place and the laminated surface is laminated and adhered on the substrate having the copper foil, a protective film is formed on the surface of the copper foil, and the surface of the internal connection terminal exposed in the cavity Plating to strengthen the connection to the copper foil, removing the protective film on the surface of the copper foil, drilling a hole to become a through hole, metallizing the inner wall of the hole and the inner wall of the cavity, unnecessary portions of the copper foil and unnecessary metal Etching is performed to expose the internal connection terminals and form an outer layer circuit having external connection terminals for connection to other substrates. After forming the plating resist to protect, a method of manufacturing a semiconductor package substrate, comprising the step of plating to strengthen the connection to the surface of the external connection terminal. 半導体チップを搭載する箇所に、キャビティを有し、そのキャビティ内に半導体チップと接続する内部接続端子を有する半導体パッケージ用基板の製造方法において、キャビティとなる開口部を有すると共に銅箔を有する基板を、キャビティの内側となる箇所に少なくとも半導体チップと接続する内部接続端子を有すると共に銅箔を有する基板の上に重ねて積層接着し、銅箔の表面に保護膜を形成し、キャビティ内に露出した内部接続端子の表面に接続を強化するためのめっきを行い、銅箔の表面の保護膜を除去し、スルーホールとなる穴をあけ、穴内壁とキャビティ内壁とを金属化し、銅箔の不要な箇所と不要な金属をエッチング除去して、内部接続端子を露出すると共に、他の基板との接続を行なう外部接続端子を有する外層回路を形成し、キャビティ部を保護するようにめっきレジストを形成した後、この外部接続端子の表面に接続を強化するためのめっきをする工程を有する半導体パッケージ用基板の製造方法。  In a method for manufacturing a substrate for a semiconductor package having a cavity at a location where a semiconductor chip is mounted and having an internal connection terminal connected to the semiconductor chip in the cavity, a substrate having an opening serving as a cavity and having a copper foil is provided. In addition, at least the internal connection terminal for connecting to the semiconductor chip is connected to the inside of the cavity and laminated on the substrate having the copper foil, and a protective film is formed on the surface of the copper foil to be exposed in the cavity. Plating to strengthen the connection on the surface of the internal connection terminal, removing the protective film on the surface of the copper foil, making a hole to be a through hole, metalizing the inner wall of the hole and the inner wall of the cavity, unnecessary copper foil Etching away locations and unnecessary metal to expose internal connection terminals and form external circuit with external connection terminals to connect to other substrates After forming the plating resist to protect the cavity, a method of manufacturing a semiconductor package substrate, comprising the step of plating to strengthen the connection to the surface of the external connection terminal. キャビティの内側となる箇所に少なくとも半導体チップと接続する内部接続端子を有する基板が、複数枚であって、下の基板の内部接続端子が露出するように、上の基板に開口部を設ける工程を有する請求項１〜３のうちいずれかに記載の半導体パッケージ用基板の製造方法。A step of providing an opening in the upper substrate so that there are a plurality of substrates having internal connection terminals connected to at least a semiconductor chip at a position inside the cavity, and the internal connection terminals of the lower substrate are exposed; The manufacturing method of the board | substrate for semiconductor packages in any one of Claims 1-3 which have. キャビティの内側となる箇所に少なくとも半導体チップと接続する内部接続端子を有する基板の裏面に、半導体チップの放熱のためのヒートシンクを貼り合わせる工程を有する請求項１〜４のうちいずれかに記載の半導体パッケージ用基板の製造方法。  5. The semiconductor according to claim 1, further comprising a step of bonding a heat sink for heat dissipation of the semiconductor chip to a back surface of the substrate having at least an internal connection terminal connected to the semiconductor chip at a position inside the cavity. A method for manufacturing a package substrate. 基板に開口部を設け、半導体チップを搭載する箇所に直接ヒートシンクが露出するように構成する工程を有する請求項５に記載の半導体パッケージ用基板の製造方法。An opening provided in the board, method of manufacturing a substrate for a semiconductor package according to claim 5 including the step configured to directly heat sink portion for mounting the semiconductor chip is exposed. 穴内壁を金属化すると共に、キャビティ内部に露出している内層回路の表面も金属化する請求項１〜６のうちいずれかに記載の半導体パッケージ用基板の製造方法。  The method for manufacturing a substrate for a semiconductor package according to any one of claims 1 to 6, wherein the inner wall of the hole is metallized, and the surface of the inner layer circuit exposed inside the cavity is also metallized. 銅箔の不要な箇所をエッチング除去するときに、キャビティ内の不要な金属化部分もエッチング除去する請求項１〜７のうちいずれかに記載の半導体パッケージ用基板の製造方法。  The method for manufacturing a substrate for a semiconductor package according to any one of claims 1 to 7, wherein when an unnecessary portion of the copper foil is removed by etching, an unnecessary metallized portion in the cavity is also removed by etching. 請求項１〜８のうちいずれかに記載の方法により製造された半導体パッケージ用基板。  A semiconductor package substrate manufactured by the method according to claim 1. 請求項１〜８のうちいずれかに記載の方法で製造された半導体パッケージ用基板のキャビティ部に半導体チップを搭載する工程を有する半導体パッケージの製造方法。  A method for manufacturing a semiconductor package, comprising a step of mounting a semiconductor chip in a cavity portion of a semiconductor package substrate manufactured by the method according to claim 1. キャビティ内の半導体チップを、封止樹脂で封止する工程を有する請求項１０に記載の半導体パッケージの製造方法。  The manufacturing method of the semiconductor package of Claim 10 which has the process of sealing the semiconductor chip in a cavity with sealing resin. 請求項１０または１１に記載の方法により製造された半導体パッケージ。  A semiconductor package manufactured by the method according to claim 10.
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