JP3334584B2 - Multilayer electronic component mounting substrate and method of manufacturing the same - Google Patents

Multilayer electronic component mounting substrate and method of manufacturing the same

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Publication number
JP3334584B2
JP3334584B2 JP33808697A JP33808697A JP3334584B2 JP 3334584 B2 JP3334584 B2 JP 3334584B2 JP 33808697 A JP33808697 A JP 33808697A JP 33808697 A JP33808697 A JP 33808697A JP 3334584 B2 JP3334584 B2 JP 3334584B2
Authority
JP
Japan
Prior art keywords
pattern
mounting
hole
wall
core
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP33808697A
Other languages
Japanese (ja)
Other versions
JPH11163528A (en
Inventor
輝代隆 塚田
直人 石田
浩二 浅野
恒 箕浦
光広 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP33808697A priority Critical patent/JP3334584B2/en
Priority to EP98954739A priority patent/EP1043921A4/en
Priority to KR10-2000-7005254A priority patent/KR100379119B1/en
Priority to PCT/JP1998/005200 priority patent/WO1999026458A1/en
Priority to US09/554,481 priority patent/US6455783B1/en
Priority to KR10-2002-7009773A priority patent/KR100393271B1/en
Publication of JPH11163528A publication Critical patent/JPH11163528A/en
Application granted granted Critical
Publication of JP3334584B2 publication Critical patent/JP3334584B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
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    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/013—Alloys
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【技術分野】本発明は，多層電子部品搭載用基板及びそ
の製造方法に関し，特にエッチング液に対する無電解め
っき膜の耐蝕性に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate for mounting a multilayer electronic component and a method of manufacturing the same, and more particularly, to the corrosion resistance of an electroless plating film to an etching solution.

【０００２】[0002]

【従来技術】近年，多層電子部品搭載用基板は，パター
ンのピッチ狭小化の傾向にある。しかも，高速に信号を
伝達させるためには，多層電子部品搭載用基板の絶縁層
の厚みを薄くしてパターン層の間隔を短くする必要があ
る。かかる要請に応じて，従来，図２２に示すごとく，
絶縁基板９１に搭載用穴９２，導通用孔及び導体パター
ン９４を形成し，これを複数枚積層することにより多層
電子部品搭載用基板を製造する方法が行われている。2. Description of the Related Art In recent years, there has been a tendency for a pattern pitch of a multilayer electronic component mounting substrate to be narrowed. In addition, in order to transmit a signal at high speed, it is necessary to reduce the thickness of the insulating layer of the multilayer electronic component mounting substrate and shorten the interval between the pattern layers. In response to such a request, conventionally, as shown in FIG.
A method for manufacturing a multilayer electronic component mounting substrate by forming a mounting hole 92, a conduction hole, and a conductor pattern 94 on an insulating substrate 91 and laminating a plurality of these holes is performed.

【０００３】[0003]

【解決しようとする課題】しかしながら，上記従来の多
層電子部品搭載用基板の製造方法においては，絶縁基板
９１にあらかじめ搭載用穴９２及び導通用孔９３を形成
する必要があるため，穴形成の際の衝撃に耐え得る厚み
が必要であった。そのため，多層電子部品搭載用基板の
薄層化は困難であった。However, in the above-mentioned conventional method for manufacturing a multilayer electronic component mounting substrate, it is necessary to previously form the mounting hole 92 and the conduction hole 93 in the insulating substrate 91. It was necessary to have a thickness that could withstand the impact of the above. Therefore, it has been difficult to reduce the thickness of the multilayer electronic component mounting substrate.

【０００４】そこで，薄い絶縁層を形成し得る方法とし
て，従来，ビルトアップ法が行われている。ビルトアッ
プ法は，図２３に示すごとく，搭載用穴９２，導通用孔
９３及び導体パターン９４を有する絶縁基板９１を準備
し，次いでその表面にプリプレグ等の絶縁層９１１を積
層する。Therefore, as a method for forming a thin insulating layer, a built-up method has been conventionally used. In the built-up method, as shown in FIG. 23, an insulating substrate 91 having a mounting hole 92, a conduction hole 93, and a conductor pattern 94 is prepared, and an insulating layer 911 such as a prepreg is laminated on the surface thereof.

【０００５】次いで，露光，現像により絶縁層９１１に
導通用孔９３１を形成し，その後絶縁層９１１の表面に
銅箔を貼着し，これをエッチングして導体パターン９４
１を形成する。このビルトアップ法では，絶縁基板を積
層する代わりに，薄い絶縁層９１１を積層するため，多
層電子部品搭載用基板の薄層化が可能となる。また，上
下に位置する導体パターン９４，９４１の間の距離が短
くなり，信号の高速伝達が可能となる。[0005] Next, conduction holes 931 are formed in the insulating layer 911 by exposure and development, and then a copper foil is adhered to the surface of the insulating layer 911, and this is etched to form the conductor pattern 94.
Form one. In this built-up method, a thin insulating layer 911 is stacked instead of an insulating substrate, so that the substrate for mounting a multilayer electronic component can be thinned. Further, the distance between the upper and lower conductor patterns 94, 941 is reduced, and high-speed signal transmission is possible.

【０００６】しかし，上記のビルトアップ法において
は，搭載用穴９２から露出した導体パターン９４が，銅
箔のエッチング液に侵蝕される場合がある。そのため，
露出した接続端子９４２へのボンディングワイヤーの接
続性が低下するおそれがある。However, in the above-described build-up method, the conductor pattern 94 exposed from the mounting hole 92 may be eroded by the etching solution for the copper foil. for that reason,
There is a possibility that the connectivity of the bonding wire to the exposed connection terminal 942 may be reduced.

【０００７】本発明はかかる従来の問題点に鑑み，パタ
ーンの層間隔を短くでき，また導通信頼性に優れた微小
な導通用孔を容易に形成することができ，かつ，エッチ
ング液に対する耐蝕性，及びボンディングワイヤーに対
する接続信頼性に優れた接続端子を有する多層電子部品
搭載用基板及びその製造方法を提供しようとするもので
ある。The present invention has been made in view of the above-mentioned conventional problems, and can reduce the distance between layers of a pattern, can easily form minute conduction holes having excellent conduction reliability, and have corrosion resistance to an etching solution. It is an object of the present invention to provide a multilayer electronic component mounting substrate having connection terminals having excellent connection reliability with respect to a bonding wire and a method of manufacturing the same.

【０００８】[0008]

【課題の解決手段】請求項１の発明は，電子部品を搭載
するための搭載用穴と，該搭載用穴の内部に露出する接
続端子と，上記搭載用穴の内壁に設けた複数の帯状の壁
面パターンと，コアパターンを設けたコア基板と，表面
パターンを設けた絶縁層とを積層してなるとともに，上
記コアパターンと上記表面パターンとを電気的に導通さ
せる導通用孔を有し，上記壁面パターンと上記コアパタ
ーンとを電気的に導通する多層電子部品搭載用基板の製
造方法において，コア基板に搭載用穴を形成し，上記コ
ア基板の表面を，上記搭載用穴の内壁を含めて金属めっ
き膜で，次いでレジスト膜で被覆した後，壁面パターン
形成用マスクを載置して，露光，レジスト膜除去，金属
めっき膜のエッチングを行うことで上記搭載用穴の内壁
に壁面パターンを形成するとともに，コア基板に，搭載
用穴に露出する位置に設けた接続端子と，導通用孔の底
部となる被覆パッドとを有するコアパターンを形成する
第１工程と，上記コア基板の表面に，上記搭載用穴を開
口させるとともに上記接続端子を露出させた状態で，絶
縁層を被覆して積層板となす第２工程と，上記搭載用穴
から露出した接続端子の表面を，無電解めっき膜により
被覆する第３工程と，上記積層板の表面に金属層を形成
する第４工程と，上記積層板の導通用孔形成部分にレー
ザー光を照射して，被覆パッドを底部とする導通用孔を
形成する第５工程と，上記導通用孔の内部に導電性被膜
を形成する第６工程と，上記金属層をエッチングして表
面パターンを形成する第７工程とからなり，上記接続端
子の表面を無電解めっき膜により被覆する第３工程の後
であってかつ上記表面パターンを形成する第７工程の前
に，上記積層板を加熱することを特徴とする多層電子部
品搭載用基板の製造方法である。According to a first aspect of the present invention, there is provided a mounting hole for mounting an electronic component, a connection terminal exposed inside the mounting hole, and a plurality of strips provided on an inner wall of the mounting hole. Wall of
The surface pattern, a core substrate provided with a core pattern, with formed by laminating and providing the surface pattern the insulating layer, have a conduction hole for electrically connecting the said core pattern and the surface pattern, the Wall pattern and above core pattern
The method of manufacturing a multilayer electronic component carrier for electrically conductive and over down to form a mounting hole in the core substrate, the co
A) Metal surface including the inner wall of the mounting hole
After coating with a resist film and a resist film,
Place the mask for formation, expose, remove resist film, metal
The inner wall of the mounting hole is etched by etching the plating film.
Forming a wall pattern on the core substrate, forming a core pattern having connection terminals provided on the core substrate at positions exposed to the mounting holes, and a covering pad serving as a bottom of the conduction hole; A second step in which the mounting holes are opened on the surface of the substrate and the connection terminals are exposed and the insulating layer is coated to form a laminate, and the surface of the connection terminals exposed from the mounting holes is formed. A third step of coating with a non-electrolytic plating film, a fourth step of forming a metal layer on the surface of the laminate, and irradiating a laser beam to a portion of the laminate where conduction holes are formed, thereby lowering the covering pad to the bottom. A fifth step of forming a conductive hole, a sixth step of forming a conductive film inside the conductive hole, and a seventh step of etching the metal layer to form a surface pattern. Electroless surface of the above connection terminal A method of manufacturing a substrate for mounting a multilayer electronic component, comprising heating the laminated board after a third step of coating with a coating film and before a seventh step of forming the surface pattern. .

【０００９】本発明において，コアパターンとは，コア
基板の表面又は内部に形成される一層又は二層以上の導
体パターンをいう。表面パターンとは，絶縁層の表面に
形成される導体パターンをいう。また，後述においてパ
ターンとは，コアパターン又は／及び表面パターンをい
う。また，本発明は，電子部品を搭載するための搭載用
穴を有するが，該搭載用穴の内壁は複数の帯状の壁面パ
ターンを有する。この壁面パターンは上記コアパターン
と電気的に導通する。 In the present invention, the core pattern refers to one or more conductor patterns formed on the surface or inside of the core substrate. The surface pattern refers to a conductor pattern formed on the surface of the insulating layer. In the following description, a pattern refers to a core pattern and / or a surface pattern. Also, the present invention is directed to a mounting device for mounting electronic components.
The mounting hole has a plurality of strip-shaped wall
Have a turn. This wall pattern is the above core pattern
Is electrically connected to

【００１０】本発明の作用及び効果について説明する。
搭載用穴の内部に露出した接続端子は，無電解めっき膜
により被覆している。無電解めっき膜の中には，接続端
子に含まれることがある銅が侵入することがある。この
銅は，エッチング液に対する耐蝕性を低下させる原因と
なる物質である。そのため，本発明においては，無電解
めっき膜を加熱し，これにより，無電解めっき膜の中の
銅を膜表面に拡散させるとともに，無電解めっき膜の自
己焼結を促し緻密な膜構造とする。The operation and effect of the present invention will be described.
The connection terminals exposed inside the mounting holes are covered with an electroless plating film. Copper which may be contained in the connection terminal may enter the electroless plating film. This copper is a substance that causes a reduction in corrosion resistance to an etching solution. Therefore, in the present invention, the electroless plating film is heated, thereby diffusing the copper in the electroless plating film to the film surface, and promoting the self-sintering of the electroless plating film to form a dense film structure. .

【００１１】このため，表面パターン形成時（第７工
程）に用いるエッチング液に対する，無電解めっき膜の
耐蝕性が向上する。従って，搭載用穴の内部に露出した
接続端子がエッチング液により侵蝕を受けることはな
い。よって，接続端子に対する，ボンディングワイヤ
ー，フリップチップ，ハンダ接続等の接合強度が向上す
る。また，接続端子の表面は，無電解めっき膜により被
覆されているため，耐蝕性に優れていると同時に，めっ
き用リードを設ける必要がなくムダな配線を必要としな
いため，電気特性が優れている。Therefore, the corrosion resistance of the electroless plating film to the etching solution used when forming the surface pattern (seventh step) is improved. Therefore, the connection terminal exposed inside the mounting hole is not eroded by the etching solution. Therefore, the bonding strength of the bonding terminal, such as a bonding wire, flip chip, or solder connection, to the connection terminal is improved. In addition, the surface of the connection terminals is covered with an electroless plating film, which is excellent in corrosion resistance. At the same time, since there is no need to provide plating leads and unnecessary wiring is required, the electrical characteristics are excellent. I have.

【００１２】また，絶縁層への導通用孔及び表面パター
ンの形成は，コア基板の表面に絶縁層を積層した後に行
う。絶縁層だけに対して予め搭載用穴，導通用孔及びパ
ターンが形成されるのではない。導通用孔及び表面パタ
ーン形成時に，絶縁層はコア基板の厚みにより補強され
ることになり，導通用孔及び表面パターンの加工時の衝
撃に十分耐えることができる。The formation of the conductive holes and the surface pattern in the insulating layer is performed after the insulating layer is laminated on the surface of the core substrate. The mounting holes, conduction holes and patterns are not formed in advance only on the insulating layer. When the conductive holes and the surface pattern are formed, the insulating layer is reinforced by the thickness of the core substrate, so that the insulating layer can sufficiently withstand the shock when processing the conductive holes and the surface pattern.

【００１３】そのため，絶縁層には，穴及びパターン形
成に必要な厚みと強度は不要である。従って，絶縁層の
厚みを従来に比べて薄くすることができる。従って，各
パターンの上下の層間隔を短くでき，信号伝達速度の高
速化を実現できる。また，搭載用穴，導通用孔及び表面
パターンは，コア基板に絶縁層を積層した比較的厚みの
ある積層板に対して形成することになるため，その形成
時の操作が容易となる。Therefore, the insulating layer does not need the thickness and strength necessary for forming holes and patterns. Therefore, the thickness of the insulating layer can be made smaller than before. Therefore, the upper and lower layer intervals of each pattern can be shortened, and the signal transmission speed can be increased. In addition, since the mounting holes, the conduction holes, and the surface pattern are formed on a relatively thick laminated board in which an insulating layer is laminated on a core substrate, the operation at the time of formation is facilitated.

【００１４】また，導通用孔形成部分に対して，レーザ
ー光をスポット的に照射すると，導通用孔形成部分の絶
縁層が焼失して，そこに導通用孔があく。この導通用孔
が導通用孔形成部分の底部を被覆する被覆パッドに到達
すると，そこで導通用孔の穿設は終了する。そのため，
深さの異なる導通用孔をレーザー照射によって容易に穿
設できる。Further, when a laser beam is spot-irradiated to the conductive hole forming portion, the insulating layer in the conductive hole forming portion is burned off, and the conductive hole is formed there. When the conductive hole reaches the covering pad that covers the bottom of the conductive hole forming portion, the formation of the conductive hole is completed there. for that reason,
Conducting holes having different depths can be easily formed by laser irradiation.

【００１５】また，レーザー光の照射によって，微細な
導通用孔を穿設することができる。また，絶縁層の絶縁
物残りもなく，導通用孔の底部を被覆する被覆パッドと
導通用孔内壁を覆う導電性被膜との電気的接続信頼性が
高い。従って，微小な導通用孔を確実にかつ容易に穿設
することができ，導通用孔のピッチ狭小化及び高密度実
装化を実現できる。よって，多量の電気信号の伝達を迅
速に行うことができる。更に，絶縁層表面における表面
パターン形成可能面積も拡大し，パターン設計の自由度
が高くなる。Further, fine conduction holes can be formed by irradiating a laser beam. In addition, there is no insulation remaining in the insulating layer, and the electrical connection reliability between the covering pad that covers the bottom of the conduction hole and the conductive film that covers the inner wall of the conduction hole is high. Therefore, minute conductive holes can be reliably and easily formed, and the pitch of the conductive holes can be reduced and high-density mounting can be realized. Therefore, a large amount of electric signals can be transmitted quickly. Further, the area on the surface of the insulating layer where a surface pattern can be formed is enlarged, and the degree of freedom in pattern design is increased.

【００１６】また，本発明の製造方法を繰り返すことに
より，表面パターンの表面にも更に表面パターン及び導
通用孔からなる積層構造を得る事ができる。なお，本発
明は，第２工程と第３工程はいずれを先に行なってもよ
い。また，第４工程と第５工程はいずれを先に行なって
もよい。要するに，無電解めっき膜形成後で表面パター
ン形成前に積層板を加熱すればよいのである。Further, by repeating the manufacturing method of the present invention, it is possible to obtain a laminated structure further comprising the surface pattern and the conductive holes on the surface of the surface pattern. In the present invention, any of the second step and the third step may be performed first. Further, any of the fourth step and the fifth step may be performed first. In short, the laminate may be heated after the electroless plating film is formed and before the surface pattern is formed.

【００１７】次に，請求項２の発明は，電子部品を搭載
するための搭載用穴と，該搭載用穴の内部に露出する接
続端子と，上記搭載用穴の内壁に設けた複数の帯状の壁
面パターンと，コアパターンを設けたコア基板と，表面
パターンを設けた絶縁層とを積層してなるとともに，上
記コアパターンと上記表面パターンとを電気的に導通さ
せる導通用孔を有し，上記壁面パターンと上記コアパタ
ーンとを電気的に導通する多層電子部品搭載用基板の製
造方法において，コア基板に搭載用穴を形成し，上記コ
ア基板の表面を，上記搭載用穴の内壁を含めて金属めっ
き膜で，次いでレジスト膜で被覆した後，壁面パターン
形成用マスクを載置して，露光，レジスト膜除去，金属
めっき膜のエッチングを行うことで上記搭載用穴の内壁
に壁面パターンを形成するとともに，コア基板に，搭載
用穴に露出する位置に設けた接続端子と，導通用孔の底
部となる被覆パッドとを有するコアパターンを形成する
第１工程と，上記コア基板の表面に，上記搭載用穴を開
口させるとともに上記接続端子を露出させた状態で，絶
縁層を被覆して積層板となす第２工程と，上記搭載用穴
から露出した接続端子の表面を，無電解めっき膜により
被覆する第３工程と，上記積層板の表面に金属層を形成
する第４工程と，上記金属層をエッチングして表面パタ
ーンを形成する第５工程と，上記積層板の導通用孔形成
部分にレーザー光を照射して，被覆パッドを底部とする
導通用孔を形成する第６工程と，上記導通用孔の内部に
導電性被膜を形成する第７工程と，上記接続端子の表面
を無電解めっき膜により被覆する第３工程の後であって
かつ上記表面パターンを形成する第５工程の煎に，上記
積層板を加熱することを特徴とする多層電子部品搭載用
基板の製造方法である。Next, a second aspect of the present invention is a mounting hole for mounting an electronic component, a connection terminal exposed inside the mounting hole, and a plurality of strips provided on an inner wall of the mounting hole. Wall of
The surface pattern, a core substrate provided with a core pattern, with formed by laminating and providing the surface pattern the insulating layer, have a conduction hole for electrically connecting the said core pattern and the surface pattern, the Wall pattern and above core pattern
The method of manufacturing a multilayer electronic component carrier for electrically conductive and over down to form a mounting hole in the core substrate, the co
A) Metal surface including the inner wall of the mounting hole
After coating with a resist film and a resist film,
Place the mask for formation, expose, remove resist film, metal
The inner wall of the mounting hole is etched by etching the plating film.
Forming a wall pattern on the core substrate, forming a core pattern having connection terminals provided on the core substrate at positions exposed to the mounting holes, and a covering pad serving as a bottom of the conduction hole; A second step in which the mounting holes are opened on the surface of the substrate and the connection terminals are exposed and the insulating layer is coated to form a laminate, and the surface of the connection terminals exposed from the mounting holes is formed. A third step of coating with a electroless plating film, a fourth step of forming a metal layer on the surface of the laminate, a fifth step of etching the metal layer to form a surface pattern, A sixth step of irradiating the conductive hole forming portion with a laser beam to form a conductive hole having the covering pad as a bottom portion, a seventh step of forming a conductive film inside the conductive hole, and the connection Electroless plating film on terminal surface A decoction of the fifth step of forming a even after the third step and the surface pattern of more covering a method for manufacturing a multilayer electronic component carrier, which comprises heating the laminate.

【００１８】請求項２の発明と請求項１の発明は，表面
パターンと導通用孔との形成順序が異なる点で相違す
る。即ち，請求項１の発明は，表面パターンを形成した
後に導通用孔を形成しているのに対して，請求項２の発
明は，導通用孔を形成した後に表面パターンを形成して
いる。The invention of claim 2 differs from the invention of claim 1 in that the order of forming the surface pattern and the conduction hole is different. That is, the invention of claim 1 forms the conduction hole after forming the surface pattern, whereas the invention of claim 2 forms the surface pattern after forming the conduction hole.

【００１９】請求項２の発明においても，表面パターン
をエッチングにより形成する前に，無電解めっき膜を加
熱している。そのため，接続端子のエッチング液による
侵蝕を防止できる。その他，請求項２の発明によれば，
請求項１の発明と同様の効果を得ることができる。な
お，請求項２の発明において，第２工程と第３工程とは
いずれを先に行なってもよい。要するに，無電解めっき
膜形成後で表面パターン形成前に積層板を加熱すればよ
いのである。In the present invention, the electroless plating film is heated before the surface pattern is formed by etching. Therefore, erosion of the connection terminal by the etchant can be prevented. In addition, according to the invention of claim 2,
The same effect as that of the first aspect can be obtained. In the invention of claim 2, any of the second step and the third step may be performed first. In short, the laminate may be heated after the electroless plating film is formed and before the surface pattern is formed.

【００２０】次に，請求項１，２の発明の詳細について
説明する。請求項３に記載のように，上記積層板の加熱
は，１５０℃〜２５０℃の温度で行うことが好ましい。
これにより，接続端子の耐蝕性を更に高めることができ
る。一方，１５０℃未満の場合には，加熱による接続端
子表面の無電解めっき膜内における金の拡散が不十分で
エッチング液により接続端子が腐蝕するおそれがある。
また，２５０℃を超える場合には，絶縁層が樹脂基板の
ときに絶縁層へのダメージが大きくなるおそれがある。
そのため，加熱処理を短時間で行わなければならない。Next, the details of the first and second aspects of the present invention will be described. Preferably, the heating of the laminate is performed at a temperature of 150 ° C to 250 ° C.
Thereby, the corrosion resistance of the connection terminal can be further improved. On the other hand, when the temperature is lower than 150 ° C., the diffusion of gold in the electroless plating film on the surface of the connection terminal due to heating is insufficient, and the connection terminal may be corroded by the etchant.
On the other hand, when the temperature exceeds 250 ° C., there is a possibility that damage to the insulating layer becomes large when the insulating layer is a resin substrate.
Therefore, the heat treatment must be performed in a short time.

【００２１】請求項４に記載のように，上記無電解めっ
き膜は，無電解Ｎｉ−Ａｕめっきあるいは無電解Ｎｉ−
Ｐｄめっきにより形成することが好ましい。これによ
り，ワイヤーボンディングが可能となる。上記無電解Ｎ
ｉ−Ａｕめっきとは，無電解めっ法により形成された，
ニッケルめっき膜及び金めっき膜をいう。上記無電解Ｎ
ｉ−Ｐｄめっきとは，無電解めっ法により形成された，
ニッケルめっき膜及びパラジウムめっき膜をいう。According to a fourth aspect of the present invention, the electroless plating film is formed by electroless Ni—Au plating or electroless Ni—
It is preferable to form by Pd plating. This enables wire bonding. The above electroless N
i-Au plating is formed by an electroless plating method.
Refers to a nickel plating film and a gold plating film. The above electroless N
i-Pd plating is formed by electroless plating.
Refers to a nickel plating film and a palladium plating film.

【００２２】請求項５に記載のように，例えば，上記接
続端子は，銅箔からなる。銅箔からなる。銅箔からなる
接続端子は，特にその表面を被覆する無電解めっき膜へ
の銅の侵入がしやすい。しかし，本発明のように接続端
子を加熱することにより，接続端子に侵入した銅を拡散
除去することができ，銅によるエッチング液への影響は
殆どない。[0022] For example, the connection terminal is made of a copper foil. Made of copper foil. The connection terminals made of copper foil are particularly prone to intrusion of copper into the electroless plating film covering the surface. However, by heating the connection terminal as in the present invention, the copper that has entered the connection terminal can be diffused and removed, and the copper has almost no effect on the etching solution.

【００２３】請求項６に記載のように，上記積層板の加
熱の後であって，上記表面パターンの形成の前に，接続
端子の表面を研磨することが好ましい。これにより，無
電解めっき膜の中の銅を除去することができる。そのた
め，銅を含むことによるエッチング液の接続端子の腐蝕
を効果的に防止できる。接続端子の研磨は，例えば，ア
ルゴンプラズマ，研磨砥粒等の機械的研磨等の方法によ
り行う事ができる。Preferably, the surface of the connection terminal is polished after the heating of the laminate and before the formation of the surface pattern. Thereby, copper in the electroless plating film can be removed. Therefore, corrosion of the connection terminal of the etching solution due to the inclusion of copper can be effectively prevented. The connection terminal can be polished by, for example, a method such as mechanical polishing of argon plasma, abrasive grains or the like.

【００２４】請求項７に記載のように，上記積層板の導
通用孔形成部分にレーザー光を照射する前に，金属層に
おける該導通用孔形成部分に，開口孔をあけておくこと
が好ましい。これにより，導通用孔の形成が容易とな
る。According to a seventh aspect of the present invention, it is preferable that an opening hole is formed in the portion of the metal layer where the conduction hole is formed before the laser beam is applied to the portion where the conduction hole is formed. . This facilitates the formation of the conduction hole.

【００２５】上記絶縁層の厚みは，３０〜１５０μｍで
あることが好ましい。これにより，パターンの層間絶縁
を確実に保持しつつ，パターンの層間隔を小さくするこ
とができ，パターン間の電気信号を迅速に伝達すること
ができる。また，多層電子部品搭載用基板の更なる薄層
化を実現できる。一方，絶縁層の厚みが３０μｍ未満の
場合には，パターン間の絶縁性を確保できないおそれが
ある。また，１５０μｍを超える場合には，パターンの
層間隔が大きくなり，電気信号の迅速な伝達を妨げるお
それがある。The thickness of the insulating layer is preferably 30 to 150 μm. As a result, it is possible to reduce the layer spacing of the pattern while reliably maintaining the interlayer insulation of the pattern, and it is possible to quickly transmit an electric signal between the patterns. Further, the thickness of the multilayer electronic component mounting substrate can be further reduced. On the other hand, if the thickness of the insulating layer is less than 30 μm, insulation between the patterns may not be ensured. On the other hand, when the thickness exceeds 150 μm, the layer spacing of the pattern becomes large, which may hinder rapid transmission of electric signals.

【００２６】上記導通用孔の直径は，３０〜３００μｍ
であることが好ましい。これにより，導通用孔の上下間
の導通を確実に行うことができ，パターン及び導通用孔
を高密度に実装することができる。一方，導通用孔の直
径が３０μｍ未満の場合には，導通用孔内にめっき液が
浸入し難くなり，導電性被膜が均一に形成されず，導通
用孔による導通がとり難くなるおそれがある。また，３
００μｍを超える場合には，導通用孔の狭ピッチ化，並
びに導通用孔及びパターンの高密度実装が困難となる場
合がある。The diameter of the hole for conduction is 30 to 300 μm.
It is preferable that As a result, conduction between the top and bottom of the conduction hole can be reliably performed, and the pattern and the conduction hole can be mounted at a high density. On the other hand, when the diameter of the conduction hole is less than 30 μm, the plating solution hardly penetrates into the conduction hole, the conductive film is not uniformly formed, and the conduction by the conduction hole may be difficult to be achieved. . Also, 3
If the thickness exceeds 00 μm, it may be difficult to reduce the pitch of the conductive holes and to mount the conductive holes and patterns at high density.

【００２７】上記コア基板は，絶縁性の基板からなる。
この基板は，パターン及び穴形成可能な機械的強度を有
することが好ましい。かかる基板は，例えば，ガラスフ
ァイバー又はガラスクロスを充填した樹脂基板を用い
る。コア基板には，コアパターン及び搭載用穴を形成す
る。コアパターンは，コア基板の表面又は内部の少なく
ともいずれかに形成する。また，コア搭載用穴は，コア
基板を貫通していてもよいし，凹状の非貫通の穴であっ
てもよい。The core substrate is an insulating substrate.
The substrate preferably has a mechanical strength capable of forming patterns and holes. As such a substrate, for example, a resin substrate filled with glass fiber or glass cloth is used. A core pattern and a mounting hole are formed in the core substrate. The core pattern is formed on at least one of the surface and the inside of the core substrate. In addition, the core mounting hole may penetrate the core substrate, or may be a concave non-through hole.

【００２８】コア基板の片面又は両面に絶縁層を被覆し
て，積層板を得る。上記絶縁層は，絶縁層は，アラミド
繊維不織布を含浸したエポキシ樹脂からなることが好ま
しい。これにより，レーザー照射の際に，絶縁層に硬直
力が働かず，絶縁層のレーザー加工性が向上する。ま
た，絶縁層は，例えば，ガラスファイバー若しくはガラ
スクロスに樹脂を含浸し半硬化させてなるプリプレグを
印刷，塗布するか，又はプリプレグのシートを敷き，そ
の後プリプレグ内の樹脂を硬化させることにより形成す
る。更に，ペースト状のソルダーレジストの印刷により
絶縁層を形成することもできる。One or both surfaces of the core substrate are coated with an insulating layer to obtain a laminated board. The insulating layer is preferably made of an epoxy resin impregnated with an aramid fiber nonwoven fabric. Thereby, the rigidity does not act on the insulating layer during laser irradiation, and the laser workability of the insulating layer is improved. The insulating layer is formed, for example, by printing and applying a prepreg obtained by impregnating a glass fiber or a glass cloth with a resin and semi-curing, or laying a prepreg sheet and then curing the resin in the prepreg. . Further, the insulating layer can be formed by printing a paste-like solder resist.

【００２９】上記導電性被膜は，例えば，銅等の導電材
料からなる，金属箔，めっき膜又はこれらの積層構造か
らなる。上記コアパターンは，金属箔，金属めっき等の
金属層のエッチングによるパターン化，又はマスクを被
覆した状態でパターン形状にめっきを析出させる方法に
より形成することができる。表面パターン形成用の金属
箔は，例えば，銅箔である。The conductive film is made of, for example, a metal foil, a plated film or a laminated structure of a conductive material such as copper. The core pattern can be formed by patterning by etching a metal layer such as a metal foil or metal plating, or by depositing plating in a pattern shape with a mask covered. The metal foil for forming the surface pattern is, for example, a copper foil.

【００３０】請求項８記載の発明は，電子部品を搭載す
るための搭載用穴と，該搭載用穴の内部に露出する接続
端子と，上記搭載用穴の内壁に設けた複数の帯状の壁面
パターンと，コアパターンを有するコア基板と，該コア
基板の表面に絶縁層を介して積層した表面パターンと，
上記コアパターンと上記表面パターンとを電気的に接続
する導通用孔とを有し，上記壁面パターンと上記コアパ
ターンとを電気的に導通する多層電子部品搭載用基板に
おいて，上記接続端子は，無電解Ｎｉ−Ａｕめっきある
いは無電解Ｎｉ−Ｐｄめっきを施し加熱された無電解め
っき膜により被覆されており，また，上記導通用孔の底
部は，被覆パッドにより被覆されていることを特徴とす
る多層電子部品搭載用基板にある。According to the present invention, there is provided a mounting hole for mounting an electronic component, a connection terminal exposed inside the mounting hole, and a plurality of strip-shaped wall surfaces provided on the inner wall of the mounting hole.
A pattern, a core substrate having a core pattern, a surface pattern laminated on the surface of the core substrate via an insulating layer,
In a multilayer electronic component mounting board having a conduction hole for electrically connecting the core pattern and the surface pattern, and electrically connecting the wall pattern and the core pattern, the connection terminal has no connection terminal. A multi-layer structure characterized by being coated with a heated electroless plating film which has been subjected to electrolytic Ni-Au plating or electroless Ni-Pd plating, and wherein the bottom of the conduction hole is covered with a coating pad. It is on the board for mounting electronic components.

【００３１】また，接続端子は，加熱処理が施された無
電解めっき膜であるため，優れた耐蝕性を発揮できる。
また，接続端子に対する，ボンディングワイヤー，フリ
ップチップ等のハンダ接合強度が向上する。また，導通
用孔の底部は，被覆パッドにより被覆されている。その
ため，導通用孔の導電性被膜と被覆パッドとの接続面積
が大きく，電気的接続信頼性に優れている。Further, since the connection terminal is a heat-treated electroless plated film, it can exhibit excellent corrosion resistance.
Further, the strength of the solder bonding of the bonding wire, flip chip, or the like to the connection terminal is improved. The bottom of the conduction hole is covered with a covering pad. Therefore, the connection area between the conductive film of the conduction hole and the coating pad is large, and the electrical connection reliability is excellent.

【００３２】また，本発明の多層電子部品搭載用基板に
よれば，導通用孔のピッチ狭小化及び高密度実装化を実
現でき，多量の電気信号の伝達を迅速に行うことができ
る。更に，絶縁層表面における表面パターン形成可能面
積も拡大し，パターン設計の自由度が高くなる。Further, according to the substrate for mounting a multilayer electronic component of the present invention, the pitch of the conductive holes can be narrowed and the mounting density can be increased, and a large amount of electric signals can be transmitted quickly. Further, the area on the surface of the insulating layer where a surface pattern can be formed is enlarged, and the degree of freedom in pattern design is increased.

【００３３】[0033]

【発明の実施の形態】実施形態例１ 本発明の実施形態例にかかる多層電子部品搭載用基板に
ついて，図１〜図１３を用いて説明する。本例の多層電
子部品搭載用基板５５は，図１に示すごとく，電子部品
８２を搭載するための搭載用穴２９と，コアパターン１
２，１３を有するコア基板２１と，コア基板２１の表面
に絶縁層２２，２３を介して積層した表面パターン１
１，１４とを有する。また，多層電子部品搭載用基板５
５は，コアパターン１２，１３と表面パターン１１，１
４とを電気的に接続する導通用孔３１，３２，３３と，
搭載用穴２９の内部に露出する接続端子１１１，１２
１，１２２，１４１とを有する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 A multilayer electronic component mounting board according to an embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 1, the multilayer electronic component mounting board 55 of this embodiment includes a mounting hole 29 for mounting an electronic component 82 and a core pattern 1.
And a surface pattern 1 laminated on the surface of the core substrate 21 with insulating layers 22 and 23 interposed therebetween.
1 and 14. In addition, the multilayer electronic component mounting substrate 5
5 is the core patterns 12, 13 and the surface patterns 11, 1
4, electrically connecting holes 31, 32, 33,
Connection terminals 111 and 12 exposed inside mounting hole 29
1, 122, and 141.

【００３４】接続端子１２１，１２２は，無電解Ｎｉ−
Ａｕめっきあるいは無電解Ｎｉ−Ｐｄめっきを施し加熱
された無電解めっき膜５により被覆されている。搭載用
穴２９の内壁には壁面パターン１５が形成されていると
ともに，その上下端は，コア基板２１の上下面に形成し
た壁面パッド１２３，１３１と接続している。また，壁
面パターン１５，壁面パッド１２３，１３１も，無電解
Ｎｉ−Ａｕめっきあるいは無電解Ｎｉ−Ｐｄめっきを施
し加熱された無電解めっき膜５により被覆されている。
導通用孔３１，３２，３３の底部は，被覆パッド１２
９，１３８，１３９により被覆されている。The connection terminals 121 and 122 are made of electroless Ni-
It is covered with a heated electroless plating film 5 which has been subjected to Au plating or electroless Ni-Pd plating. For mounting
The wall pattern 15 is formed on the inner wall of the hole 29 , and the upper and lower ends thereof are connected to wall pads 123 and 131 formed on the upper and lower surfaces of the core substrate 21. In addition, the wall pattern 15 and the wall pads 123 and 131 are also covered with the heated electroless plating film 5 which has been subjected to electroless Ni-Au plating or electroless Ni-Pd plating.
The bottom of the conduction holes 31, 32, 33 is
9,138,139.

【００３５】表面パターン１１は，図１，図２に示すご
とく，外部接続用の半田ボール６３を接合するための接
合パッド１１５を有している。多層電子部品搭載用基板
５５の下面には，搭載用穴２９を被覆するよう放熱板８
１が接着されている。多層電子部品搭載用基板５５の表
面は，ソルダーレジスト２５により被覆されている。As shown in FIGS. 1 and 2, the surface pattern 11 has bonding pads 115 for bonding the solder balls 63 for external connection. The lower surface of the multilayer electronic component mounting board 55 is provided with a heat sink 8 so as to cover the mounting holes 29.
1 is adhered. The surface of the multilayer electronic component mounting board 55 is covered with the solder resist 25.

【００３６】コアパターン１２は，図１，図３に示すご
とく，導通用孔３１の底部となる被覆パッド１２９と導
通用孔３３の中腹部壁面を囲む補強ランド１２８と，接
続端子１２１，１２２と，接続端子１２２と接続する壁
面パッド１２３とを有する。As shown in FIGS. 1 and 3, the core pattern 12 includes a cover pad 129 serving as the bottom of the conduction hole 31, a reinforcing land 128 surrounding the middle abdominal wall of the conduction hole 33, connection terminals 121 and 122, , And a wall pad 123 connected to the connection terminal 122.

【００３７】次に，上記多層電子部品搭載用基板の製造
方法について説明する。 第１工程 まず，コア基板としての絶縁基板を準備する。この絶縁
基板は，エポキシ系，ビスマレイミドトリアジン系，ポ
リイミド系等の樹脂に，ガラスファイバー若しくはガラ
スクロスを含浸したものである。Next, a method of manufacturing the above-mentioned multilayer electronic component mounting board will be described. First Step First, an insulating substrate as a core substrate is prepared. This insulating substrate is made by impregnating a resin such as an epoxy resin, a bismaleimide triazine resin, or a polyimide resin with glass fiber or glass cloth.

【００３８】次いで，図４に示すごとく，コア基板２１
の両面に銅箔１を貼着する。次いで，搭載用穴形成用の
搭載用穴２９をルーターにより穿設する。次いで，搭載
用穴２９の内壁を含めて，コア基板２１の表面に化学銅
めっき及び電気銅めっきにより金属めっき膜１００を被
覆する。Next, as shown in FIG.
The copper foil 1 is stuck on both sides of. Next, a mounting hole 29 for forming a mounting hole is formed by a router. Next, the metal plating film 100 is coated on the surface of the core substrate 21 including the inner wall of the mounting hole 29 by chemical copper plating and electrolytic copper plating.

【００３９】次いで，金属めっき膜１００の表面に，ネ
ガ型感光性樹脂からなるレジスト膜７を被覆する。次い
で，コア基板２１の上面，下面に，壁面パターン形成用
のマスク４０を被覆する。このマスク４０は，搭載用穴
２９を被覆する部分に，壁面パターン非形成部分を露光
するためのスリット４１を有する。次いで，マスク４０
により被覆したコア基板２１に，散乱光４を照射する。
これにより，レジスト膜７における，壁面パターン非形
成部分及び壁面パッド非形成部分が感光する。Next, the surface of the metal plating film 100 is coated with a resist film 7 made of a negative photosensitive resin. Next, the upper and lower surfaces of the core substrate 21 are covered with a mask 40 for forming a wall surface pattern. The mask 40 has a slit 41 for exposing a portion where the wall surface pattern is not formed, in a portion covering the mounting hole 29. Next, the mask 40
The scattered light 4 is applied to the core substrate 21 covered by the above.
As a result, portions of the resist film 7 where no wall pattern is formed and where no wall pad is formed are exposed.

【００４０】次いで，マスク４０を取り去り，レジスト
膜７を現像して，壁面パターン非形成部分及び壁面パッ
ド非形成部分におけるレジスト膜７を除去する。次い
で，レジスト膜７から露出した金属めっき膜１００及び
銅箔１をエッチングにより除去する。これにより，図５
に示すごとく，搭載用穴２９の内壁にコア基板２１の露
出面２９１が形成されて該露出面２９１の間に壁面パタ
ーン１５が形成される。また，搭載用穴２９の周縁部に
壁面パッド間の露出面２９２が形成される。次いで，コ
ア基板２１の表面に残っているレジスト膜７をアルカリ
溶液により除去して，銅箔１を露出させる。Next, the mask 40 is removed, and the resist film 7 is developed to remove the resist film 7 in the portion where the wall pattern is not formed and the portion where the wall pad is not formed. Next, the metal plating film 100 and the copper foil 1 exposed from the resist film 7 are removed by etching. As a result, FIG.
As shown in (1), the exposed surface 291 of the core substrate 21 is formed on the inner wall of the mounting hole 29, and the wall surface pattern 15 is formed between the exposed surfaces 291. Further, an exposed surface 292 between the wall surface pads is formed on the peripheral portion of the mounting hole 29. Next, the resist film 7 remaining on the surface of the core substrate 21 is removed with an alkaline solution to expose the copper foil 1.

【００４１】次いで，図６に示すごとく，コアパターン
形成用のマスク４２を載置する。搭載用穴２９は，マス
ク４２により被覆する。次いで，コア基板２１の表面の
銅箔１をエッチングする。これにより，図７，図３に示
すごとく，コア基板２１の上面に，接続端子１２１，１
２２，壁面パッド１２３，被覆パッド１２９，補強ラン
ド１２８を有するコアパターン１２を形成する。Next, as shown in FIG. 6, a mask 42 for forming a core pattern is placed. The mounting hole 29 is covered with a mask 42. Next, the copper foil 1 on the surface of the core substrate 21 is etched. Thus, as shown in FIGS. 7 and 3, the connection terminals 121, 1
A core pattern 12 having 22, a wall pad 123, a covering pad 129, and a reinforcing land 128 is formed.

【００４２】被覆パッド１２９は，図３に示すごとく，
導通用孔３１の底部となる位置に円盤形状に形成された
パターンである。また，補強ランド１２８は，導通用孔
３３の側壁を囲むことになるリング状のパターンであ
る。また，コア基板２１の下面には，図７，図１に示す
ごとく，円盤状の被覆パッド１３８，１３９及び壁面パ
ッド１３１を有するコアパターン１３を形成する。The covering pad 129 is, as shown in FIG.
This is a pattern formed in a disc shape at a position to be the bottom of the conduction hole 31. The reinforcement land 128 is a ring-shaped pattern that surrounds the side wall of the conduction hole 33. On the lower surface of the core substrate 21, a core pattern 13 having disk-shaped covering pads 138 and 139 and wall pads 131 is formed as shown in FIGS.

【００４３】第２工程 次いで，図８に示すごとく，コア基板２１の表面に，ガ
ラスクロスに樹脂を含浸して半硬化状態となしたプリプ
レグを積層して絶縁層２２，２３を形成して，積層板２
を得る。また，プリプレグの代わりにアラミド繊維不織
布を含浸したエポキシ樹脂を用いてもよい。絶縁層２
２，２３の厚みはそれぞれ３０〜１５０μｍとする。こ
れらの絶縁層を構成するプリプレグには，あらかじめ穴
あけ加工を施して，上面側の絶縁層２２には搭載用穴２
９よりも大きく開口した開口穴２９６を形成し，下面側
の絶縁層２３に搭載用穴２９よりも小さく開口した開口
穴２９７を形成する。Second Step Next, as shown in FIG. 8, on the surface of the core substrate 21, a prepreg in a semi-cured state obtained by impregnating a glass cloth with a resin is laminated to form insulating layers 22 and 23. Laminated board 2
Get. Further, an epoxy resin impregnated with an aramid fiber nonwoven fabric may be used instead of the prepreg. Insulating layer 2
The thickness of each of Nos. 2 and 23 is 30 to 150 μm. Drilling is performed in advance on the prepregs constituting these insulating layers, and mounting holes 2 are formed in the insulating layer 22 on the upper surface side.
An opening 296 that is larger than 9 is formed, and an opening 297 that is smaller than the mounting hole 29 is formed in the insulating layer 23 on the lower surface side.

【００４４】第３工程 次いで，図９に示すごとく，搭載用穴２９の内部に露出
した接続端子１２１，１２２，及び壁面パターン１５及
び壁面パッド１２３，１３１の表面に，無電解Ｎｉ−Ａ
ｕめっきあるいは無電解Ｎｉ−Ｐｄめっきを施して無電
解めっき膜５を形成する。Third Step Next, as shown in FIG. 9, the surface of the connection terminals 121 and 122 and the wall pattern 15 and the wall pads 123 and 131 exposed inside the mounting hole 29 is electroless Ni-A.
The electroless plating film 5 is formed by performing u plating or electroless Ni-Pd plating.

【００４５】第４工程 次いで，図１０に示すごとく，積層板２の上面及び下面
に，プリプレグからなる接着シート２４を介して銅箔１
を貼着する。このとき，銅箔１により搭載用穴２９を被
覆する。次いで，図１１に示すごとく，エッチングによ
り，銅箔１の導通用孔形成部分３１０，３２０，３３０
に開口孔１０を形成する。Fourth Step Next, as shown in FIG. 10, the copper foil 1 was placed on the upper and lower surfaces of the laminate 2 via an adhesive sheet 24 made of prepreg.
Affix. At this time, the mounting hole 29 is covered with the copper foil 1. Then, as shown in FIG. 11, the conductive hole forming portions 310, 320, 330 of the copper foil 1 are etched.
The opening hole 10 is formed.

【００４６】第５工程 次いで，積層板２の上記導通用孔形成部分に，炭酸ガス
レーザー，エキシマレーザー等のレーザー光４５を照射
する。Fifth Step Next, a laser beam 45 such as a carbon dioxide laser or an excimer laser is applied to the portion of the laminate 2 where the conductive holes are formed.

【００４７】レーザー光４５の照射による導通用孔の形
成は，積層板２をその高いエネルギーにより焼失除去さ
せていき，順次内方へ孔をあけていく。そして，レーザ
ー光４５の先端が導通用孔形成部分３１０，３２０，３
３０の底部を被覆する被覆パッド１２９，１３８，１３
９に到達したときに，これらにより反射されてここで孔
形成の進行が停止する。これにより，直径３０〜３００
μｍの導通用孔３１〜３３が穿設される。このとき，積
層板２の表面全体は，導通用孔形成部分３１０，３２
０，３３０を除いて，銅箔１により被覆されているた
め，レーザー光４５による積層板２の損傷はない。In the formation of the conduction hole by irradiation with the laser beam 45, the laminated plate 2 is burned and removed by its high energy, and holes are sequentially formed inward. Then, the tip of the laser beam 45 is connected to the conduction hole forming portions 310, 320, 3.
Cover pads 129, 138, 13 covering the bottom of 30
At the time of reaching 9, the light is reflected by these, and the progress of hole formation is stopped here. As a result, a diameter of 30 to 300
μm conduction holes 31 to 33 are formed. At this time, the entire surface of the laminated plate 2 is
Except for 0,330, the laminate 2 is not damaged by the laser beam 45 because it is covered with the copper foil 1.

【００４８】第６工程 次いで，図１２（ａ）に示すごとく，導通用孔３１〜３
３の内壁を含めて，積層板２の表面に，化学銅めっき，
パラジウム触媒付与及び電気銅めっきを行い，導電性被
膜６７を被覆する。このとき，深い導通用孔３３は，壁
面の中央位置にリング状の補強ランド１２８が形成され
ているため，補強ランド１２８と表面パターン１１との
間，補強ランド１２８と導体パターン１３との間が短く
なり導電部材の間隔が短縮化されて，化学めっきが析出
しやすい状態となり導通用孔３３の内壁に導電性被膜６
７が均一に形成される。Sixth step Next, as shown in FIG.
Chemical copper plating on the surface of the laminate 2 including the inner wall of
Palladium catalyst application and electrolytic copper plating are performed to cover the conductive film 67. At this time, since the ring-shaped reinforcing land 128 is formed in the deep conductive hole 33 at the center position of the wall surface, the space between the reinforcing land 128 and the surface pattern 11 and the space between the reinforcing land 128 and the conductor pattern 13 are formed. As a result, the distance between the conductive members is shortened, and the chemical plating is easily deposited.
7 are formed uniformly.

【００４９】次いで，図１２（ｂ）に示すごとく，積層
板２を１５０℃，６０分間以上，又は１６０℃で３０分
間以上加熱する。Next, as shown in FIG. 12B, the laminate 2 is heated at 150 ° C. for 60 minutes or more, or at 160 ° C. for 30 minutes or more.

【００５０】第７工程 次いで，図１３に示すごとく，銅箔１にエッチングを施
して，接続端子１１１，及び半田ボール接合用の接合パ
ッド１１５を有する表面パターン１１と，接続端子１４
１を有する表面パターン１４とを形成する。Seventh Step Next, as shown in FIG. 13, the copper foil 1 is etched to form a surface pattern 11 having connection terminals 111 and bonding pads 115 for solder ball bonding.
1 is formed.

【００５１】その後，図１に示すごとく，積層板２の表
面に，ソルダーレジスト２５を被覆する。次いで，接合
パッド１１５，接続端子１１１，１４１，１２１，１２
２，壁面パッド１２３，１３１，壁面パターン１５の表
面に，ニッケル／金めっき膜６を施す。次いで，接合パ
ッド１１５の表面に，半田ボール６３を接合する。ま
た，積層板２の下面に，搭載用穴２９を被覆するよう
に，エポキシ系等の絶縁性樹脂からなる接着剤８５によ
り，金属製の放熱板８１を接着する。これにより，放熱
板８１の上面は，搭載用穴２９の底部を構成することに
なり，その表面には銀ペースト等の接着剤８３により電
子部品８２が接着される。以上により，本例の多層電子
部品搭載用基板５５が得られる。Thereafter, as shown in FIG. 1, the surface of the laminate 2 is coated with a solder resist 25. Next, the bonding pad 115, the connection terminals 111, 141, 121, 12
2. A nickel / gold plating film 6 is applied to the surfaces of the wall surface pads 123, 131 and the wall surface pattern 15. Next, the solder ball 63 is bonded to the surface of the bonding pad 115. Further, a metal heat radiating plate 81 is bonded to the lower surface of the laminated plate 2 with an adhesive 85 made of an insulating resin such as an epoxy resin so as to cover the mounting hole 29. As a result, the upper surface of the heat radiating plate 81 forms the bottom of the mounting hole 29, and the electronic component 82 is adhered to the surface by the adhesive 83 such as a silver paste. As described above, the multilayer electronic component mounting board 55 of this example is obtained.

【００５２】次に，本例の作用及び効果について説明す
る。図９に示すごとく，搭載用穴２９の内部に露出した
接続端子１２１，１２２は，無電解めっき膜５により被
覆した後，図１２（ｂ）に示すごとく，これを加熱して
いる。加熱により，無電解めっき膜５の中に含まれてい
ることがある銅が膜表面に拡散する。また，無電解めっ
き膜５の自己焼結を促し緻密な膜構造となる。このた
め，表面パターン形成時（図１３）に用いるエッチング
液に対する，無電解めっき膜５の耐蝕性が向上する。従
って，搭載用穴２９の内部に露出した接続端子１２１，
１２２の表面が侵蝕を受けることはない。よって，接続
端子に対する，ボンディングワイヤー８４の接合強度が
向上する。Next, the operation and effect of this embodiment will be described. As shown in FIG. 9, the connection terminals 121 and 122 exposed inside the mounting hole 29 are covered with the electroless plating film 5 and then heated as shown in FIG. By heating, copper which may be contained in the electroless plating film 5 diffuses to the film surface. Further, self-sintering of the electroless plating film 5 is promoted, and a dense film structure is obtained. Therefore, the corrosion resistance of the electroless plating film 5 with respect to the etching solution used when forming the surface pattern (FIG. 13) is improved. Therefore, the connection terminals 121 exposed inside the mounting holes 29,
The surface of 122 is not eroded. Therefore, the bonding strength of the bonding wire 84 to the connection terminal is improved.

【００５３】なお，本例においては壁面パターン１５及
び壁面パッド１２３，１３１を形成したが，これらを形
成しなくてもよい。また，コア基板２１の上面，下面に
絶縁層２２，２３を介して表面パターン１１，１４を積
層したが，コア基板の片面だけに絶縁層を介して表面パ
ターンを設けてもよい。In the present embodiment, the wall pattern 15 and the wall pads 123 and 131 are formed, but they need not be formed. Although the surface patterns 11 and 14 are laminated on the upper and lower surfaces of the core substrate 21 via the insulating layers 22 and 23, the surface pattern may be provided on only one surface of the core substrate via the insulating layer.

【００５４】実施形態例２ 本例においては，図１４に示すごとく，積層板２に導通
用孔３１，３２，３３を穿設する第５工程を行った後
に，図１５に示すごとくめっき処理により金属層１０１
を形成する第４工程を行っている。Embodiment 2 In this embodiment, as shown in FIG. 14, after performing a fifth step of forming conductive holes 31, 32, and 33 in the laminated board 2, plating is performed by plating as shown in FIG. Metal layer 101
Is performed in the fourth step.

【００５５】即ち，実施形態例１における製造方法の中
の第１工程から第３工程を行なった後に第５工程を行
い，更に第４工程を行う。積層板の加熱は，第４工程の
前，第５工程の前又は後に行う。加熱条件は，１５０
℃，６０分間以上，又は１６０℃で３０分間以上とす
る。次いで，実施形態例１の第６工程から第７工程を行
なう。その他は，実施形態例１と同様である。本例にお
いても，実施形態例１と同様の効果を得ることができ
る。That is, after performing the first to third steps in the manufacturing method in the first embodiment, the fifth step is performed, and then the fourth step is performed. The heating of the laminate is performed before the fourth step, before or after the fifth step. The heating condition is 150
C., 60 minutes or more, or 160 ° C., 30 minutes or more. Next, the sixth to seventh steps of the first embodiment are performed. Others are the same as the first embodiment. Also in this example, the same effect as in the first embodiment can be obtained.

【００５６】実施形態例３ 本例にかかる多層電子部品搭載用基板５６は，図１６に
示すごとく，コア基板２１の内部にもコアパターン１９
を設けている点を除いて，実施形態例１と同様の構成で
ある。Embodiment 3 A multi-layer electronic component mounting board 56 according to the present embodiment has a core pattern 19 inside the core board 21 as shown in FIG.
The configuration is the same as that of the first embodiment except that the first embodiment is provided.

【００５７】即ち，多層電子部品搭載用基板５６は，図
１６に示すごとく，コアパターン１２，１３，１９を有
するコア基板２１と，その上面，下面に設けた絶縁層２
２，２３と，絶縁層２２，２３の表面に設けた表面パタ
ーン１１，１４と，搭載用穴２９の内部に露出する接続
端子１１１，１２１，１２２，１４１とを有する。That is, as shown in FIG. 16, the multilayer electronic component mounting board 56 includes a core board 21 having core patterns 12, 13, and 19 and insulating layers 2 provided on the upper and lower surfaces thereof.
2 and 23, surface patterns 11 and 14 provided on the surfaces of the insulating layers 22 and 23, and connection terminals 111, 121, 122 and 141 exposed inside the mounting holes 29.

【００５８】コア基板２１の内部に設けたコアパターン
１９は，導通用孔３０１，３３の底部となる被覆パッド
１９８，１９９を有し，壁面パターン１５及び壁面パッ
ド１２３を通じてコア基板２１の表面に設けた接続端子
１２２と電気的に接続している（図２参照）。The core pattern 19 provided inside the core substrate 21 has covering pads 198 and 199 serving as bottoms of the conduction holes 301 and 33, and is provided on the surface of the core substrate 21 through the wall pattern 15 and the wall pad 123. (See FIG. 2).

【００５９】表面パターン１１は，外部接続用の半田ボ
ール６３を接合するための接合パッド１１５を有してい
る。コアパターン１２は，実施形態例１と同様に導通用
孔３３の内壁の周縁を囲むリング状の補強ランド１２８
と，導通用孔３１の底部を被覆する被覆パッド１２９と
接続端子１２１と，壁面パターン１５と接続する壁面パ
ッド１２３と接続端子１２２とを有している（図２参
照）。なお，本例の多層電子部品搭載用基板の平面構造
は，実施形態例１における図２に示される構造と同様で
ある。The surface pattern 11 has bonding pads 115 for bonding the solder balls 63 for external connection. The core pattern 12 is a ring-shaped reinforcing land 128 surrounding the periphery of the inner wall of the conduction hole 33 as in the first embodiment.
And a cover pad 129 and a connection terminal 121 for covering the bottom of the conduction hole 31, and a wall pad 123 and a connection terminal 122 connected to the wall pattern 15 (see FIG. 2). Note that the planar structure of the multilayer electronic component mounting board of this example is the same as the structure shown in FIG.

【００６０】接続端子１２１，１２２は，電子部品８２
とボンディングワイヤー８４により電気的に接続するた
めの端子であり，無電解Ｎｉ−Ａｕめっきあるいは無電
解Ｎｉ−Ｐｄめっきを施し加熱された無電解めっき膜５
により被覆されている。本例の多層電子部品搭載用基板
５６は，ソルダーレジスト２５を有する。The connection terminals 121 and 122 are
And a terminal for electrically connecting with the bonding wire 84, the electroless plated film 5 heated by applying electroless Ni-Au plating or electroless Ni-Pd plating.
Covered with The multilayer electronic component mounting board 56 of the present embodiment has the solder resist 25.

【００６１】次に，上記多層電子部品搭載用基板の製造
方法について説明する。 第１工程 まず，図１７に示すごとく，絶縁層２１０の間にコアパ
ターン１９を形成することのほかは，実施形態例１と同
様にコアパターン１２，１３及びコア基板２１を形成す
る。次いで，コア基板２１にレーザー照射により導通用
孔３０１を穿設しその内壁を導電性被膜６７により被覆
する。Next, a method for manufacturing the above-mentioned substrate for mounting a multilayer electronic component will be described. First Step First, as shown in FIG. 17, core patterns 12, 13 and a core substrate 21 are formed in the same manner as in the first embodiment, except that a core pattern 19 is formed between insulating layers 210. Next, a conduction hole 301 is formed in the core substrate 21 by laser irradiation, and the inner wall thereof is covered with a conductive film 67.

【００６２】第２工程 次いで，図１８（ａ）に示すごとく，コア基板２１の搭
載用穴２９を開口させた状態で，コア基板２１の上面及
び下面に絶縁層２２，２３を被覆する。Second Step Next, as shown in FIG. 18A, the upper and lower surfaces of the core substrate 21 are covered with insulating layers 22 and 23 with the mounting hole 29 of the core substrate 21 opened.

【００６３】第３工程 次いで，絶縁層２２，２３の表面に，プリプレグからな
る接着シート２４を介して銅箔１を接着する。なお，接
着シート２４及び銅箔１には，積層前に予め搭載用穴２
９を露出させるための開口穴１０をあけておく。これに
より，積層板２となす。Third Step Next, the copper foil 1 is adhered to the surfaces of the insulating layers 22 and 23 via an adhesive sheet 24 made of prepreg. The adhesive sheet 24 and the copper foil 1 are provided with mounting holes 2 before lamination.
An opening hole 10 for exposing 9 is made. Thus, a laminated plate 2 is formed.

【００６４】第４工程 次に，搭載用穴２９の内部に露出した接続端子１２１，
１２２，及び壁面パターン１５及び壁面パッド１２３，
１３１の表面に，無電解Ｎｉ−Ａｕめっきあるいは無電
解Ｎｉ−Ｐｄめっきを施して無電解めっき膜５を形成す
る。次いで，図１８（ｂ）に示すごとく，積層板を１５
０℃，６０分間以上，又は１６０℃で３０分間以上加熱
する。Fourth Step Next, the connection terminals 121 exposed inside the mounting holes 29,
122, and the wall pattern 15 and the wall pad 123,
The surface of 131 is subjected to electroless Ni—Au plating or electroless Ni—Pd plating to form an electroless plated film 5. Next, as shown in FIG.
Heat at 0 ° C. for 60 minutes or more, or at 160 ° C. for 30 minutes or more.

【００６５】第５工程 次いで，図１９に示すごとく，銅箔１をエッチングし
て，表面パターン１１，１４を形成する。Fifth Step Next, as shown in FIG. 19, the copper foil 1 is etched to form surface patterns 11 and 14.

【００６６】第６工程 次いで，図２０に示すごとく，積層板２にレーザー光を
照射して，導通用孔３３〜３３を穿設する。次いで，搭
載用穴２９の内壁を含めて，コア基板２１の表面に化学
銅めっき膜８を被覆する。Sixth Step Next, as shown in FIG. 20, the laminated plate 2 is irradiated with a laser beam to form conduction holes 33 to 33. Next, the surface of the core substrate 21 including the inner wall of the mounting hole 29 is coated with the chemical copper plating film 8.

【００６７】第７工程 次いで，図２１に示すごとく，導通用孔３１〜３３を除
く積層板２の全表面にマスクを被覆し，導通用孔３１〜
３３の内壁に電気めっき処理により導電性被膜６７を形
成する。次いで，マスクを除去するとともに，導電性被
膜６７より露出した化学銅めっき膜８をソフトエッチン
グ等により除去する。Seventh Step Next, as shown in FIG. 21, a mask is coated on the entire surface of the laminate 2 except for the conduction holes 31 to 33, and the conduction holes 31 to 33 are covered.
A conductive film 67 is formed on the inner wall of the electrode 33 by electroplating. Next, the mask is removed, and the chemical copper plating film 8 exposed from the conductive film 67 is removed by soft etching or the like.

【００６８】その後，図１６に示すごとく，実施形態例
１と同様に，ソルダーレジスト２５の形成，放熱板８１
の接着，及び半田ボール６３の接合を行い，多層電子部
品搭載用基板５６を得る。Thereafter, as shown in FIG. 16, the solder resist 25 is formed and the heat radiating plate 81 is formed in the same manner as in the first embodiment.
And bonding of the solder balls 63 is performed to obtain a multilayer electronic component mounting substrate 56.

【００６９】次に，本例の作用及び効果について説明す
る。本例においては，図１８（ｂ）に示すごとく，接続
端子１２１，１２３，１４１を加熱した後に，図１９に
示すごとく，銅箔のエッチング処理により表面パターン
１１，１４を形成している。そのため，エッチング液に
よる接続端子の腐食を抑制できる。なお，本例において
は，図１８（ａ）に示すごとく，表面パターン１１，１
４を銅箔１のエッチングにより形成しているが，積層板
２の全面を銅めっき膜により被覆しこれをエッチングす
ることにより形成することもできる。Next, the operation and effect of this embodiment will be described. In this example, as shown in FIG. 18B, after heating the connection terminals 121, 123, 141, the surface patterns 11, 14 are formed by etching the copper foil as shown in FIG. Therefore, corrosion of the connection terminal due to the etching solution can be suppressed. In this example, as shown in FIG.
4 is formed by etching the copper foil 1, but it can also be formed by covering the entire surface of the laminate 2 with a copper plating film and etching the same.

【００７０】[0070]

【発明の効果】本発明によれば，パターンの層間隔を短
くでき，また導通信頼性に優れた微小な導通用孔を容易
に形成することができ，かつ，エッチング液に対する耐
蝕性，及びボンディングワイヤーに対する接続信頼性に
優れた接続端子を有する多層電子部品搭載用基板及びそ
の製造方法を提供することができる。According to the present invention, it is possible to shorten the interval between layers of a pattern, easily form minute conduction holes having excellent conduction reliability, and provide corrosion resistance to an etching solution and bonding. It is possible to provide a multilayer electronic component mounting board having connection terminals having excellent connection reliability to a wire and a method for manufacturing the same.

【図面の簡単な説明】[Brief description of the drawings]

【図１】実施形態例１における，多層電子部品搭載用基
板の断面図。FIG. 1 is a cross-sectional view of a multilayer electronic component mounting board according to a first embodiment.

【図２】実施形態例１における，多層電子部品搭載用基
板の平面図。FIG. 2 is a plan view of the multilayer electronic component mounting board according to the first embodiment.

【図３】実施形態例１における，コアパターンを示すた
めのコア基板の平面図。FIG. 3 is a plan view of a core substrate for illustrating a core pattern according to the first embodiment.

【図４】実施形態例１の多層電子部品搭載用基板の製造
方法における，壁面パターンの形成方法を示すためのコ
ア基板の断面説明図。FIG. 4 is an explanatory cross-sectional view of the core substrate for illustrating a method of forming a wall pattern in the method of manufacturing the multilayer electronic component mounting substrate according to the first embodiment;

【図５】図４に続く，壁面パターンを形成したコア基板
の斜視図。FIG. 5 is a perspective view of the core substrate on which a wall pattern is formed, following FIG. 4;

【図６】図５に続く，コアパターンを形成する方法を示
すためのコア基板の斜視図。FIG. 6 is a perspective view of the core substrate for illustrating a method of forming a core pattern, following FIG. 5;

【図７】図６に続く，コアパターンを形成したコア基板
の断面図。FIG. 7 is a sectional view of the core substrate on which a core pattern is formed, following FIG. 6;

【図８】図７に続く，積層板の断面図。FIG. 8 is a sectional view of the laminated plate, following FIG. 7;

【図９】図８に続く，接続端子に無電解めっき膜を形成
した積層板の断面図。FIG. 9 is a cross-sectional view of the laminated board in which an electroless plating film is formed on a connection terminal, following FIG. 8;

【図１０】図９に続く，銅箔を貼着した積層板の断面
図。FIG. 10 is a cross-sectional view of the laminated plate to which the copper foil is adhered, following FIG. 9;

【図１１】図１０に続く，導通用孔の形成方法を示すた
めの積層板の断面図。FIG. 11 is a cross-sectional view of the laminate, illustrating a method of forming the conduction holes, following FIG. 10;

【図１２】図１１に続く，導通用孔の内壁に導電性被膜
を形成した積層板の断面図（図１２（ａ）），及び加熱
工程を示す説明図（図１２（ｂ））。12 is a cross-sectional view (FIG. 12 (a)) of the laminated plate in which a conductive film is formed on the inner wall of the conduction hole, following FIG. 11, and an explanatory view showing a heating step (FIG. 12 (b)).

【図１３】図１２に続く，表面パターンを形成した積層
板の断面図。FIG. 13 is a cross-sectional view of the laminate having the surface pattern formed thereon, following FIG. 12;

【図１４】実施形態例２における，多層電子部品搭載用
基板の製造方法における，導通用孔の形成方法を示すた
めの積層板の断面図。FIG. 14 is a cross-sectional view of a laminated board for illustrating a method of forming conduction holes in a method of manufacturing a multilayer electronic component mounting board according to a second embodiment.

【図１５】図１５に続く，金属層により被覆された積層
板の断面図。FIG. 15 is a sectional view of the laminate covered with a metal layer, following FIG. 15;

【図１６】実施形態例３の多層電子部品搭載用基板の断
面図。FIG. 16 is a sectional view of a multilayer electronic component mounting board according to a third embodiment.

【図１７】実施形態例３の多層電子部品搭載用基板の製
造方法における，コア基板の断面図。FIG. 17 is a sectional view of a core substrate in a method for manufacturing a multilayer electronic component mounting board according to a third embodiment;

【図１８】図１７に続く，積層板の断面図（図１８
（ａ）），及び加熱工程を示す説明図（図１８
（ｂ））。18 is a sectional view of the laminated plate following FIG. 17 (FIG. 18);
(A)) and an explanatory view showing a heating step (FIG. 18)
(B)).

【図１９】図１８に続く，表面パターンを形成したコア
基板の断面図。FIG. 19 is a sectional view of the core substrate on which the surface pattern is formed, following FIG. 18;

【図２０】図１９に続く，導通用孔及び化学銅めっき膜
を形成した積層板の断面図。FIG. 20 is a cross-sectional view of the laminated plate on which conductive holes and a chemical copper plating film are formed, following FIG. 19;

【図２１】図２０に続く，導通用孔の内壁に導電性被膜
を被覆した積層板の断面図。FIG. 21 is a cross-sectional view of the laminate in which an inner wall of the conduction hole is covered with a conductive film, following FIG. 20;

【図２２】従来例における，多層電子部品搭載用基板の
製造方法を示すための説明図。FIG. 22 is an explanatory view showing a method of manufacturing a multilayer electronic component mounting board in a conventional example.

【図２３】他の従来例における，多層電子部品搭載用基
板の製造方法を示すための説明図。FIG. 23 is an explanatory view showing a method of manufacturing a multilayer electronic component mounting board in another conventional example.

【符号の説明】[Explanation of symbols]

１．．．銅箔， １０．．．開口孔， １１，１４．．．表面パターン， １２，１３，１９．．．コアパターン， １５．．．壁面パターン， １０１．．．金属層， １１１，１２１，１２２，１４１．．．接続端子， １１５．．．接合パッド， １２３，１３１．．．壁面パッド １２８．．．補強ランド， １２９，１３８，１３９，１９８，１９９．．．被覆パ
ッド， ２．．．積層板， ２１．．．コア基板， ２２，２３，２１０．．．絶縁層， ２４．．．接着シート， ２５．．．ソルダーレジスト， ２９．．．搭載用穴， ３１，３２，３３，３０１．．．導通用孔， ３１０，３２０，３３０．．．導通用孔形成部分， ５．．．無電解めっき膜， ５５，５６．．．多層電子部品搭載用基板， ６．．．ニッケル／金めっき膜， ３．．．半田ボール， ６７．．．導電性被膜， ８１．．．放熱板， ８２．．．電子部品， ８４．．．ボンディングワイヤー，1. . . Copper foil, 10. . . Opening holes, 11,14. . . Surface pattern, 12,13,19. . . Core pattern, 15. . . Wall pattern, 101. . . Metal layers, 111, 121, 122, 141. . . Connection terminal, 115. . . Bonding pad, 123, 131. . . Wall pad 128. . . Reinforcement land, 129, 138, 139, 198, 199. . . Covering pad, 2. . . Laminate, 21. . . Core substrate, 22, 23, 210. . . Insulating layer, 24. . . Adhesive sheet, 25. . . Solder resist, 29. . . Mounting holes, 31, 32, 33, 301. . . Conduction holes, 310, 320, 330. . . 4. Portion forming hole for conduction, . . Electroless plating film, 55, 56. . . 5. Multi-layer electronic component mounting board, . . 2. Nickel / gold plating film, . . Solder ball, 67. . . Conductive coating, 81. . . Heat sink, 82. . . Electronic components, 84. . . Bonding wire,

───────────────────────────────────────────────────── フロントページの続き (72)発明者 近藤 光広 岐阜県大垣市河間町３丁目200番地 イ ビデン株式会社 河間工場内 審査官 中川 隆司 (56)参考文献 特開 平７−106769（ＪＰ，Ａ) 特開 平９−246724（ＪＰ，Ａ) 特開 平７−312476（ＪＰ，Ａ) 特開 平８−37378（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H05K 3/46 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Mitsuhiro Kondo, Inventor 3-200, Kawamacho, Ogaki-shi, Gifu Ibiden Co., Ltd. Kawama Plant Examiner Takashi Nakagawa (56) References JP-A-9-246724 (JP, A) JP-A-7-312476 (JP, A) JP-A-8-37378 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H05K 3/46

Claims (9)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 電子部品を搭載するための搭載用穴と，
該搭載用穴の内部に露出する接続端子と，上記搭載用穴
の内壁に設けた複数の帯状の壁面パターンと，コアパタ
ーンを設けたコア基板と，表面パターンを設けた絶縁層
とを積層してなるとともに，上記コアパターンと上記表
面パターンとを電気的に導通させる導通用孔を有し，上
記壁面パターンと上記コアパターンとを電気的に導通す
る多層電子部品搭載用基板の製造方法において， コア基板に搭載用穴を形成し，上記コア基板の表面を，
上記搭載用穴の内壁を含めて金属めっき膜で，次いでレ
ジスト膜で被覆した後，壁面パターン形成用マスクを載
置して，露光，レジスト膜除去，金属めっき膜のエッチ
ングを行うことで上記搭載用穴の内壁に壁面パターンを
形成するとともに， コア基板に，搭載用穴に露出する位置に設けた接続端子
と，導通用孔の底部となる被覆パッドとを有するコアパ
ターンを形成する第１工程と， 上記コア基板の表面に，上記搭載用穴を開口させるとと
もに上記接続端子を露出させた状態で，絶縁層を被覆し
て積層板となす第２工程と， 上記搭載用穴から露出した接続端子の表面を，無電解め
っき膜により被覆する第３工程と， 上記積層板の表面に金属層を形成する第４工程と， 上記積層板の導通用孔形成部分にレーザー光を照射し
て，被覆パッドを底部とする導通用孔を形成する第５工
程と， 上記導通用孔の内部に導電性被膜を形成する第６工程
と， 上記金属層をエッチングして表面パターンを形成する第
７工程とからなり， 上記接続端子の表面を無電解めっき膜により被覆する第
３工程の後であってかつ上記表面パターンを形成する第
７工程の前に，上記積層板を加熱することを特徴とする
多層電子部品搭載用基板の製造方法。A mounting hole for mounting an electronic component;
A connection terminal exposed inside the mounting hole, a plurality of strip-shaped wall patterns provided on the inner wall of the mounting hole, a core substrate provided with a core pattern, and an insulating layer provided with a surface pattern are laminated. A method for manufacturing a multilayer electronic component mounting board having a conduction hole for electrically connecting the core pattern and the surface pattern, and electrically connecting the wall pattern and the core pattern. A mounting hole is formed in the core substrate, and the surface of the core substrate is
After covering the inner wall of the mounting hole with a metal plating film and then a resist film, a mask for forming a wall pattern is placed, and exposure, removal of the resist film, and etching of the metal plating film are performed. Forming a wall pattern on the inner wall of the hole, and forming a core pattern on the core substrate, the connection pattern being provided at a position exposed to the mounting hole and a covering pad serving as a bottom of the conduction hole. A second step of forming a laminated board by covering an insulating layer with the mounting holes being opened and the connection terminals being exposed on the surface of the core substrate; and a connection exposed from the mounting holes. A third step of coating the surface of the terminal with an electroless plating film, a fourth step of forming a metal layer on the surface of the laminate, and irradiating a laser beam to a portion of the laminate where a conductive hole is formed. Coating pad A fifth step of forming a conductive hole serving as a bottom part, a sixth step of forming a conductive film inside the conductive hole, and a seventh step of etching the metal layer to form a surface pattern. And heating the laminated board after a third step of coating the surface of the connection terminal with an electroless plating film and before a seventh step of forming the surface pattern. Manufacturing method of mounting substrate. 【請求項２】 電子部品を搭載するための搭載用穴と，
該搭載用穴の内部に露出する接続端子と，上記搭載用穴
の内壁に設けた複数の帯状の壁面パターンと，コアパタ
ーンを設けたコア基板と，表面パターンを設けた絶縁層
とを積層してなるとともに，上記コアパターンと上記表
面パターンとを電気的に導通させる導通用孔を有し，上
記壁面パターンと上記コアパターンとを電気的に導通す
る多層電子部品搭載用基板の製造方法において， コア基板に搭載用穴を形成し，上記コア基板の表面を，
上記搭載用穴の内壁を含めて金属めっき膜で，次いでレ
ジスト膜で被覆した後，壁面パターン形成用マスクを載
置して，露光，レジスト膜除去，金属めっき膜のエッチ
ングを行うことで上記搭載用穴の内壁に壁面パターンを
形成するとともに， コア基板に，搭載用穴に露出する位置に設けた接続端子
と，導通用孔の底部となる被覆パッドとを有するコアパ
ターンを形成する第１工程と， 上記コア基板の表面に，上記搭載用穴を開口させるとと
もに上記接続端子を露出させた状態で，絶縁層を被覆し
て積層板となす第２工程と， 上記搭載用穴から露出した接続端子の表面を，無電解め
っき膜により被覆する第３工程と， 上記積層板の表面に金属層を形成する第４工程と， 上記金属層をエッチングして表面パターンを形成する第
５工程と， 上記積層板の導通用孔形成部分にレーザー光を照射し
て，被覆パッドを底部とする導通用孔を形成する第６工
程と， 上記導通用孔の内部に導電性被膜を形成する第７工程
と， 上記接続端子の表面を無電解めっき膜により被覆する第
３工程の後であってかつ上記表面パターンを形成する第
５工程の煎に，上記積層板を加熱することを特徴とする
多層電子部品搭載用基板の製造方法。2. A mounting hole for mounting an electronic component,
A connection terminal exposed inside the mounting hole, a plurality of strip-shaped wall patterns provided on the inner wall of the mounting hole, a core substrate provided with a core pattern, and an insulating layer provided with a surface pattern are laminated. A method for manufacturing a multilayer electronic component mounting board having a conduction hole for electrically connecting the core pattern and the surface pattern, and electrically connecting the wall pattern and the core pattern. A mounting hole is formed in the core substrate, and the surface of the core substrate is
After covering the inner wall of the mounting hole with a metal plating film and then a resist film, a mask for forming a wall pattern is placed, and exposure, removal of the resist film, and etching of the metal plating film are performed. Forming a wall pattern on the inner wall of the hole, and forming a core pattern on the core substrate, the connection pattern being provided at a position exposed to the mounting hole and a covering pad serving as a bottom of the conduction hole. A second step of forming a laminated board by covering an insulating layer with the mounting holes being opened and the connection terminals being exposed on the surface of the core substrate; and a connection exposed from the mounting holes. A third step of coating the surface of the terminal with an electroless plating film, a fourth step of forming a metal layer on the surface of the laminate, a fifth step of etching the metal layer to form a surface pattern, Up A sixth step of irradiating a laser beam to the conductive hole forming portion of the laminate to form a conductive hole with the covering pad at the bottom, and a seventh step of forming a conductive film inside the conductive hole. Heating the laminated board after the third step of covering the surface of the connection terminal with an electroless plating film and in the fifth step of forming the surface pattern. Manufacturing method of mounting substrate. 【請求項３】 請求項１又は２において，上記積層板の
加熱は，１５０℃〜２５０℃の温度で行うことを特徴と
する多層電子部品搭載用基板の製造方法。3. The method according to claim 1, wherein the heating of the laminate is performed at a temperature of 150 ° C. to 250 ° C. 【請求項４】 請求項１〜３のいずれか１項において，
上記無電解めっき膜は，無電解Ｎｉ−Ａｕめっきあるい
は無電解Ｎｉ−Ｐｄめっきにより形成することを特徴と
する多層電子部品搭載用基板の製造方法。4. The method according to claim 1, wherein:
The method for manufacturing a substrate for mounting a multilayer electronic component, wherein the electroless plating film is formed by electroless Ni-Au plating or electroless Ni-Pd plating. 【請求項５】 請求項１〜４のいずれか１項において，
上記接続端子は，銅箔からなることを特徴とする多層電
子部品搭載用基板の製造方法。5. The method according to claim 1, wherein:
A method for manufacturing a multilayer electronic component mounting board, characterized in that the connection terminals are made of copper foil. 【請求項６】 請求項１〜５のいずれか１項において，
上記積層板の加熱の後であって，上記表面パターンの形
成の前に，接続端子の表面を研磨することを特徴とする
多層電子部品搭載用基板の製造方法。6. The method according to claim 1, wherein:
A method of manufacturing a substrate for mounting a multilayer electronic component, comprising: polishing a surface of a connection terminal after heating the laminate and before forming the surface pattern. 【請求項７】 請求項１〜６のいずれか１項において，
上記積層板の導通用孔形成部分にレーザー光を照射する
前に，金属層における該導通用孔形成部分に，開口孔を
あけておくことを特徴とする多層電子部品搭載用基板の
製造方法。7. The method according to claim 1, wherein:
A method for manufacturing a substrate for mounting a multilayer electronic component, characterized in that an opening hole is formed in the conductive hole forming portion of the metal layer before irradiating the conductive hole forming portion of the laminate with a laser beam. 【請求項８】 電子部品を搭載するための搭載用穴と，
該搭載用穴の内部に露出する接続端子と，上記搭載用穴
の内壁に設けた複数の帯状の壁面パターンと，コアパタ
ーンを有するコア基板と，該コア基板の表面に絶縁層を
介して積層した表面パターンと，上記コアパターンと上
記表面パターンとを電気的に接続する導通用孔とを有
し，上記壁面パターンと上記コアパターンとを電気的に
導通する多層電子部品搭載用基板において， 上記接続端子は，無電解Ｎｉ−Ａｕめっきあるいは無電
解Ｎｉ−Ｐｄめっきを施し加熱された無電解めっき膜に
より被覆されており， また，上記導通用孔の底部は，被覆パッドにより被覆さ
れていることを特徴とする多層電子部品搭載用基板。8. A mounting hole for mounting an electronic component,
A connection terminal exposed inside the mounting hole;
A plurality of strip-shaped wall patterns provided on the inner wall of the substrate, a core substrate having a core pattern, a surface pattern laminated on the surface of the core substrate via an insulating layer, and electrically connecting the core pattern and the surface pattern to each other. Yes the conduction holes to be connected
In the multi-layer electronic component mounting board for electrically connecting the wall pattern and the core pattern, the connection terminal is formed by electroless Ni-Au plating or electroless Ni-Pd plating and heated electroless plating. A multilayer electronic component mounting substrate, wherein the substrate is covered with a film, and a bottom of the conduction hole is covered with a covering pad. 【請求項９】 請求項８において，上記接続端子は，銅
箔からなることを特徴とする多層電子部品搭載用基板。9. The substrate for mounting a multilayer electronic component according to claim 8, wherein said connection terminals are made of copper foil.
JP33808697A 1997-11-19 1997-11-21 Multilayer electronic component mounting substrate and method of manufacturing the same Expired - Fee Related JP3334584B2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP33808697A JP3334584B2 (en) 1997-11-21 1997-11-21 Multilayer electronic component mounting substrate and method of manufacturing the same
EP98954739A EP1043921A4 (en) 1997-11-19 1998-11-19 Multilayer printed wiring board and method for manufacturing the same
KR10-2000-7005254A KR100379119B1 (en) 1997-11-19 1998-11-19 Multilayer printed wiring board and method for manufacturing the same
PCT/JP1998/005200 WO1999026458A1 (en) 1997-11-19 1998-11-19 Multilayer printed wiring board and method for manufacturing the same
US09/554,481 US6455783B1 (en) 1997-11-19 1998-11-19 Multilayer printed wiring board and method for manufacturing the same
KR10-2002-7009773A KR100393271B1 (en) 1997-11-19 1998-11-19 Method for manufacturing a multilayer electronic component mounting substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33808697A JP3334584B2 (en) 1997-11-21 1997-11-21 Multilayer electronic component mounting substrate and method of manufacturing the same

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Publication Number Publication Date
JPH11163528A JPH11163528A (en) 1999-06-18
JP3334584B2 true JP3334584B2 (en) 2002-10-15

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JP4840628B2 (en) * 2000-07-24 2011-12-21 日立化成工業株式会社 Semiconductor package substrate manufacturing method, semiconductor package manufacturing method using the method, and semiconductor package substrate and semiconductor package using these methods
WO2003003427A1 (en) * 2001-06-29 2003-01-09 Xanoptix, Inc. Opto-electronic device integration
DE102006060432A1 (en) * 2006-12-20 2008-06-26 Epcos Ag Electrical component and external contact of an electrical component

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