JP2002043454A - Method for manufacturing substrate for semiconductor package, method for manufacturing semiconductor package using the method, and substrate for semiconductor package and semiconductor package using these methods - Google Patents
Method for manufacturing substrate for semiconductor package, method for manufacturing semiconductor package using the method, and substrate for semiconductor package and semiconductor package using these methodsInfo
- Publication number
- JP2002043454A JP2002043454A JP2000221615A JP2000221615A JP2002043454A JP 2002043454 A JP2002043454 A JP 2002043454A JP 2000221615 A JP2000221615 A JP 2000221615A JP 2000221615 A JP2000221615 A JP 2000221615A JP 2002043454 A JP2002043454 A JP 2002043454A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- cavity
- semiconductor package
- internal connection
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体パッケージ
用基板の製造方法とその方法を用いた半導体パッケージ
の製造方法及びこれらの方法を用いた半導体パッケージ
用基板と半導体パッケージに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor package substrate, a method for manufacturing a semiconductor package using the method, and a semiconductor package substrate and a semiconductor package using these methods.
【０００２】[0002]
【従来の技術】従来、半導体チップを搭載する箇所に、
キャビティを有し、そのキャビティ内に半導体チップと
接続する内部接続端子を有する半導体パッケージ用基板
の製造方法においては、図４（ａ）に示すように、キャ
ビティとなる開口部を有する基板１１０を、キャビティ
の内側となる箇所に少なくとも半導体チップと接続する
内部接続端子１２１を有する基板１２０の上に重ね、さ
らにそのキャビティとなる開口部を有する基板１１０の
上に、銅箔１０５を貼り合わせた基板であって内部接続
端子１２１を保護するための基板１００を重ねて積層接
着し、図４（ｂ）に示すように、スルーホールとなる穴
１３０をあけ、図４（ｃ）に示すように、穴１３０の内
壁を金属化してスルーホール１３１とし、銅箔１０５の
不要な箇所をエッチング除去して外層回路１２６を形成
した後に、図４（ｄ）に示すように、内部接続端子１２
１を保護するための基板１００に、キャビティを形成す
るための開口部をザグリ加工などで形成し、外層回路１
２６の表面にソルダーレジスト１２７を形成し、キャビ
ティ内に露出した内部接続端子１２１の表面に、接続を
強化するためのめっき１２２を行うことが知られてい
る。2. Description of the Related Art Conventionally, in a place where a semiconductor chip is mounted,
In a method for manufacturing a semiconductor package substrate having a cavity and having internal connection terminals connected to a semiconductor chip in the cavity, as shown in FIG. A substrate in which a copper foil 105 is laminated on a substrate 120 having at least an internal connection terminal 121 connected to a semiconductor chip at a location inside a cavity, and further on a substrate 110 having an opening serving as the cavity. Then, a substrate 100 for protecting the internal connection terminals 121 is overlaid and adhered, and a hole 130 serving as a through hole is formed as shown in FIG. 4B, and a hole 130 is formed as shown in FIG. After the inner wall of 130 is metallized to form a through hole 131 and unnecessary portions of copper foil 105 are removed by etching to form outer layer circuit 126, FIG. As shown in), internal connection terminals 12
An opening for forming a cavity is formed in the substrate 100 for protecting the substrate 1 by counterbore processing or the like, and the outer layer circuit 1 is formed.
It is known that a solder resist 127 is formed on the surface of the internal connection terminal 26, and plating 122 for strengthening the connection is performed on the surface of the internal connection terminal 121 exposed in the cavity.
【０００３】[0003]
【発明が解決しようとする課題】このような半導体パッ
ケージ用基板の製造は、キャビティを形成するための開
口部をザグリ加工で形成すると、ザグリ加工のときの加
工誤差があるので、その加工誤差分を、図４（ｅ）や図
４（ｆ）に示すように、接続端子１２１の面積を広くし
たり、外層回路１２６の形成を避けなければならないの
で、近年の発達に伴う半導体パッケージの小型化にはあ
まり適していないという課題がある。In the manufacture of such a semiconductor package substrate, when an opening for forming a cavity is formed by counterbore processing, there is a processing error in the counterbore processing. As shown in FIGS. 4E and 4F, the area of the connection terminal 121 must be increased and the formation of the outer layer circuit 126 must be avoided. Has a problem that it is not very suitable.
【０００４】更に、外層回路１２６にも内部接続端子１
２１と同じ種類の、接続を強化するためのめっき１２２
を行うことがあり、その場合には、外層回路１２６とめ
っき電極との距離と、内部接続端子１２１とめっき電極
との距離が異なるため、めっきの膜厚バラツキが大き
く、内部接続端子１２１上のめっき厚さは薄く、外層回
路１２６上のめっき厚さは厚くなる傾向があり、内部接
続端子１２１のワイヤボンディング性が低下し、外層回
路１２６の半田接続信頼性が低下するという課題があ
る。Further, the internal connection terminal 1 is also provided in the outer layer circuit 126.
Plating 122 of the same type as 21 for strengthening the connection
In this case, the distance between the outer layer circuit 126 and the plating electrode is different from the distance between the internal connection terminal 121 and the plating electrode. The plating thickness tends to be thin, and the plating thickness on the outer layer circuit 126 tends to be thicker, so that there is a problem that the wire bonding property of the internal connection terminal 121 is reduced and the solder connection reliability of the outer layer circuit 126 is reduced.
【０００５】本発明は、小型化にすぐれ、外層回路にも
内部接続端子と同じ種類の、接続を強化するめっきを行
う場合でも、めっきの膜厚のばらつきが少なく、内部接
続端子のワイヤボンディング性に優れ、かつ外部接続端
子の接続信頼性に優れた半導体パッケージ用基板の製造
方法とその方法を用いた半導体パッケージの製造方法及
びこれらの方法を用いた半導体パッケージ用基板と半導
体パッケージを提供することを目的とする。The present invention is excellent in miniaturization and has a small variation in plating film thickness even when plating the same type as the internal connection terminals on the outer layer circuit to enhance the connection. To provide a method for manufacturing a semiconductor package substrate excellent in reliability and excellent in connection reliability of external connection terminals, a method for manufacturing a semiconductor package using the method, and a semiconductor package substrate and a semiconductor package using these methods With the goal.
【０００６】[0006]
【課題を解決するための手段】本発明は以下のことを特
徴とする。 （１）半導体チップを搭載する箇所に、キャビティを有
し、そのキャビティ内に半導体チップと接続する内部接
続端子を有する半導体パッケージ用基板の製造方法にお
いて、キャビティとなる開口部を有すると共に銅箔を有
する基板を、キャビティの内側となる箇所に少なくとも
半導体チップと接続する内部接続端子を有する基板の上
に重ねて積層接着し、銅箔の表面に保護膜を形成し、キ
ャビティ内に露出した内部接続端子の表面に接続を強化
するためのめっきを行い、銅箔の表面の保護膜を除去
し、スルーホールとなる穴をあけ、穴内壁とキャビティ
内壁とを金属化し、銅箔の不要な箇所と不要な金属をエ
ッチング除去して、内部接続端子を露出すると共に外層
回路を形成する工程を有する半導体パッケージ用基板の
製造方法。 （２）半導体チップを搭載する箇所に、キャビティを有
し、そのキャビティ内に半導体チップと接続する内部接
続端子を有する半導体パッケージ用基板の製造方法にお
いて、キャビティとなる開口部を有する基板を、キャビ
ティの内側となる箇所に少なくとも半導体チップと接続
する内部接続端子を有すると共に銅箔を有する基板の上
に重ねて積層接着し、銅箔の表面に保護膜を形成し、キ
ャビティ内に露出した内部接続端子の表面に接続を強化
するためのめっきを行い、銅箔の表面の保護膜を除去
し、スルーホールとなる穴をあけ、穴内壁とキャビティ
内壁とを金属化し、銅箔の不要な箇所と不要な金属をエ
ッチング除去して、内部接続端子を露出すると共に外層
回路を形成する工程を有する半導体パッケージ用基板の
製造方法。 （３） 半導体チップを搭載する箇所に、キャビティを
有し、そのキャビティ内に半導体チップと接続する内部
接続端子を有する半導体パッケージ用基板の製造方法に
おいて、キャビティとなる開口部を有すると共に銅箔を
有する基板を、キャビティの内側となる箇所に少なくと
も半導体チップと接続する内部接続端子を有すると共に
銅箔を有する基板の上に重ねて積層接着し、銅箔の表面
に第１の保護膜を形成し、キャビティ内に露出した内部
接続端子の表面に接続を強化するためのめっきを行い、
銅箔の表面に保護膜を形成し、キャビティ内に露出した
内部接続端子の表面に接続を強化するためのめっきを行
い、銅箔の表面の保護膜を除去し、スルーホールとなる
穴をあけ、穴内壁とキャビティ内壁とを金属化し、銅箔
の不要な箇所と不要な金属をエッチング除去して、内部
接続端子を露出すると共に外層回路を形成する工程を有
する半導体パッケージ用基板の製造方法。 （４）キャビティの内側となる箇所に少なくとも半導体
チップと接続する内部接続端子を有する基板が、複数枚
であって、下の基板の内部接続端子が露出するように、
上の基板に開口部を設ける工程を有する（１）〜（３）
に記載の半導体パッケージ用基板の製造方法。 （５）キャビティの内側となる箇所に少なくとも半導体
チップと接続する内部接続端子を有する基板の裏面に、
半導体チップの放熱のためのヒートシンクを貼り合わせ
る工程を有する（１）〜（４）のうちいずれかに記載の
半導体パッケージ用基板の製造方法。 （６）基板に開口部を設け、半導体チップを搭載する箇
所に直接ヒートシンクが露出するように構成する工程を
有する（５）に記載の半導体パッケージ用基板の製造方
法。 （７）穴内壁を金属化すると共に、キャビティ内部に露
出している内層回路の表面も金属化する（１）〜（６）
のうちいずれかに記載の半導体パッケージ用基板の製造
方法。 （８）銅箔の不要な箇所をエッチング除去するときに、
キャビティ内の不要な金属化部分もエッチング除去する
（１）〜（７）のうちいずれかに記載の半導体パケージ
用基板の製造方法。 （９）外層回路が、他の基板との接続を行う外部接続端
子を有する（１）〜（８）のうちいずれかに記載の半導
体パッケージ用基板。 （１０）外部接続端子を形成した後に、その表面に接続
を強化する金属を形成する（９）に記載の半導体パッケ
ージ用基板の製造方法。 （１１）（１）〜（１０）のうちいずれかに記載の方法
により製造された半導体パッケージ用基板。 （１２）（１）〜（１０）のうちいずれかに記載の方法
で製造された半導体パッケージ用基板のキャビティ部に
半導体チップを搭載する工程を有する半導体パッケージ
の製造方法。 （１３）キャビティ内の半導体チップを、封止樹脂で封
止する工程を有する（１２）に記載の半導体パッケージ
の製造方法。 （１４）（１２）または（１３）に記載の方法により製
造された半導体パッケージ。The present invention has the following features. (1) In a method of manufacturing a semiconductor package substrate having a cavity at a position where a semiconductor chip is mounted and having an internal connection terminal connected to the semiconductor chip in the cavity, a method for manufacturing a substrate having an opening serving as a cavity and using copper foil A substrate having an internal connection terminal connected to at least a semiconductor chip at a location inside the cavity is laminated and adhered, a protective film is formed on the surface of the copper foil, and the internal connection exposed in the cavity is formed. Plating to strengthen the connection on the surface of the terminal, remove the protective film on the surface of the copper foil, drill holes to be through holes, metalize the inner wall of the hole and the inner wall of the cavity, and remove unnecessary parts of the copper foil. A method for manufacturing a substrate for a semiconductor package, comprising: a step of exposing unnecessary internal metals to expose internal connection terminals and forming an external circuit. (2) In a method for manufacturing a semiconductor package substrate having a cavity at a position where a semiconductor chip is mounted and having an internal connection terminal connected to the semiconductor chip in the cavity, the substrate having an opening serving as a cavity may be provided with a cavity. Having at least an internal connection terminal connected to the semiconductor chip at a location on the inside of the substrate, and laminating and bonding on a substrate having a copper foil, forming a protective film on the surface of the copper foil, and exposing the internal connection exposed in the cavity. Plating to strengthen the connection on the surface of the terminal, remove the protective film on the surface of the copper foil, drill holes to be through holes, metalize the inner wall of the hole and the inner wall of the cavity, and remove unnecessary parts of the copper foil. A method for manufacturing a substrate for a semiconductor package, comprising: a step of exposing unnecessary internal metals to expose internal connection terminals and forming an external circuit. (3) In a method of manufacturing a semiconductor package substrate having a cavity at a place where a semiconductor chip is mounted and having an internal connection terminal connected to the semiconductor chip in the cavity, the method includes the step of forming an opening serving as a cavity and using a copper foil. A substrate having at least an internal connection terminal connected to the semiconductor chip at a location inside the cavity and being laminated and adhered on a substrate having a copper foil, forming a first protective film on the surface of the copper foil. , Plating on the surface of the internal connection terminal exposed in the cavity to strengthen the connection,
A protective film is formed on the surface of the copper foil, plating is performed on the surface of the internal connection terminals exposed in the cavity to strengthen the connection, the protective film on the surface of the copper foil is removed, and holes are formed as through holes. A method for manufacturing a substrate for a semiconductor package, comprising the steps of: metalizing an inner wall of a hole and an inner wall of a cavity; etching and removing unnecessary portions and unnecessary metal of a copper foil to expose internal connection terminals and form an outer layer circuit. (4) There are a plurality of substrates having internal connection terminals connected to the semiconductor chip at a position inside the cavity so that the internal connection terminals of the lower substrate are exposed.
(1) to (3) including a step of providing an opening in the upper substrate
3. The method for manufacturing a semiconductor package substrate according to claim 1. (5) On the back surface of the substrate having at least an internal connection terminal connected to the semiconductor chip at a location inside the cavity,
The method for manufacturing a semiconductor package substrate according to any one of (1) to (4), further comprising a step of attaching a heat sink for heat dissipation of the semiconductor chip. (6) The method for manufacturing a substrate for a semiconductor package according to (5), further comprising the step of providing an opening in the substrate so that the heat sink is directly exposed at a position where the semiconductor chip is mounted. (7) The inner wall of the hole is metallized, and the surface of the inner layer circuit exposed inside the cavity is also metallized (1) to (6).
The method for manufacturing a substrate for a semiconductor package according to any one of the above. (8) When removing unnecessary portions of copper foil by etching,
The method for manufacturing a semiconductor package substrate according to any one of (1) to (7), wherein unnecessary metallized portions in the cavity are also removed by etching. (9) The semiconductor package substrate according to any one of (1) to (8), wherein the outer layer circuit has an external connection terminal for connecting to another substrate. (10) The method of manufacturing a semiconductor package substrate according to (9), wherein after forming the external connection terminal, a metal for strengthening the connection is formed on the surface of the external connection terminal. (11) A semiconductor package substrate manufactured by the method according to any one of (1) to (10). (12) A method of manufacturing a semiconductor package, comprising: mounting a semiconductor chip in a cavity of a semiconductor package substrate manufactured by the method according to any one of (1) to (10). (13) The method of manufacturing a semiconductor package according to (12), further comprising a step of sealing the semiconductor chip in the cavity with a sealing resin. (14) A semiconductor package manufactured by the method according to (12) or (13).
【０００７】[0007]
【発明の実施の形態】本発明によって、半導体チップを
搭載する箇所に、キャビティを有し、そのキャビティ内
に半導体チップと接続する内部接続端子を有する半導体
パッケージ用基板を製造するには、図１（ａ）に示すよ
うに、キャビティとなる開口部を有すると共に銅箔１５
を有する基板１０を、キャビティの内側となる箇所に少
なくとも半導体チップと接続する内部接続端子２１を有
する基板２０の上に重ねて積層接着し、図１（ｂ）に示
すように、銅箔１５の表面に保護膜１３を形成し、キャ
ビティ内に露出した内部接続端子２１の表面に接続を強
化するためのめっき２２を行い、図１（ｃ）に示すよう
に、銅箔１５の表面の保護膜１３を除去し、スルーホー
ル３１となる穴３０をあけ、図１（ｄ）に示すように、
穴３０の内壁とキャビティの内壁とを金属化して、スル
ーホール３１を形成して、図１（ｅ）に示すように、銅
箔１５の不要な箇所とキャビティ内の不要な金属とをエ
ッチング除去して、外層回路２６を形成することと、内
部接続端子２１の露出とを行うことができる。この外層
回路２６は、上記の説明では、キャビティとなる開口部
を有する基板１０に貼り合わされた銅箔１５を加工して
形成しているが、銅箔１５は、かならずしもキャビティ
となる開口部を有する基板１０の側に貼り合わされてい
なくてもよく、図３（ａ）に示すように、内部接続端子
を有する基板２０に貼り合わされていてもよく、また、
図３（ｂ）に示すように、その両方の基板に貼り合わさ
れていてもよい。また、キャビティの内側となる箇所に
少なくとも半導体チップと接続する内部接続端子２１を
有する基板２０は、図３（ｃ）に示すように、複数枚で
あってもよく、その場合には、下の基板２０１の内部接
続端子２１が露出するように、上の基板２０２に開口部
を設けなければならない。DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the present invention, a method for manufacturing a semiconductor package substrate having a cavity at a place where a semiconductor chip is mounted and having internal connection terminals connected to the semiconductor chip in the cavity is shown in FIG. (A) As shown in FIG.
Is laminated and adhered on a substrate 20 having an internal connection terminal 21 connected to at least a semiconductor chip at a location inside the cavity, and as shown in FIG. A protective film 13 is formed on the surface, and plating 22 for strengthening the connection is performed on the surface of the internal connection terminal 21 exposed in the cavity. As shown in FIG. 1C, the protective film on the surface of the copper foil 15 is formed. 13 is removed, and a hole 30 serving as a through hole 31 is formed. As shown in FIG.
The inner wall of the hole 30 and the inner wall of the cavity are metallized to form a through hole 31, and as shown in FIG. 1E, unnecessary portions of the copper foil 15 and unnecessary metal in the cavity are removed by etching. Thus, the formation of the outer layer circuit 26 and the exposure of the internal connection terminal 21 can be performed. In the above description, the outer layer circuit 26 is formed by processing the copper foil 15 bonded to the substrate 10 having an opening serving as a cavity, but the copper foil 15 necessarily has an opening serving as a cavity. It may not be bonded to the substrate 10 side, but may be bonded to a substrate 20 having internal connection terminals as shown in FIG.
As shown in FIG. 3B, it may be bonded to both substrates. Further, as shown in FIG. 3 (c), the substrate 20 having at least the internal connection terminal 21 connected to the semiconductor chip at a position inside the cavity may be a plurality of substrates. An opening must be provided in the upper substrate 202 so that the internal connection terminals 21 of the substrate 201 are exposed.
【０００８】この半導体パッケージ用基板には、キャビ
ティの内側となる箇所に少なくとも半導体チップと接続
する内部接続端子２１を有する基板２０の裏面に、図３
（ｄ）に示すように、半導体チップの放熱のためのヒー
トシンク４１を貼り合わせることができ、さらに、図３
（ｅ）に示すように、基板２０に開口部を設け、半導体
チップを搭載する箇所に直接ヒートシンク４１が露出す
るように構成することもできる。このヒートシンク４１
の形状は、図３（ｄ）に示すような金属板でもよく、ま
た、図３（ｅ）に示すような突出部を有するものでもよ
い。This semiconductor package substrate has a structure shown in FIG. 3 on the back surface of a substrate 20 having at least an internal connection terminal 21 connected to a semiconductor chip at a location inside the cavity.
As shown in FIG. 3D, a heat sink 41 for heat dissipation of the semiconductor chip can be attached.
As shown in (e), an opening may be provided in the substrate 20 so that the heat sink 41 is directly exposed at a position where the semiconductor chip is mounted. This heat sink 41
May be a metal plate as shown in FIG. 3 (d), or may have a protrusion as shown in FIG. 3 (e).
【０００９】本発明の、キャビティとなる開口部を有す
ると共に銅箔１５を有する基板１０には、配線板に通常
に使用する銅張り積層板を用いることができ、キャビテ
ィとなる開口部は、金型による打ち抜き、あるいは、ル
ータによる加工などによって形成することができる。A copper-clad laminate commonly used for a wiring board can be used for the substrate 10 having an opening serving as a cavity and a copper foil 15 according to the present invention, and the opening serving as a cavity is made of gold. It can be formed by punching with a mold or processing with a router.
【００１０】キャビティの内側となる箇所に少なくとも
半導体チップと接続する内部接続端子２１を有する基板
２０には、上記のキャビティとなる開口部を有すると共
に銅箔１５を有する基板１０と同様に、配線板に通常に
使用する銅張り積層板を用いることができ、内部接続端
子２１は、その銅張り積層板の銅箔の上に内部接続端子
２１の形状にエッチングレジストを形成して、不要な箇
所をエッチング除去して形成することができる。A substrate 20 having at least an internal connection terminal 21 connected to a semiconductor chip at a location inside the cavity has a wiring board similar to the substrate 10 having an opening serving as a cavity and having a copper foil 15. A copper-clad laminate commonly used can be used for the internal connection terminals 21. An etching resist is formed in the shape of the internal connection terminals 21 on the copper foil of the copper-clad laminate, and unnecessary portions are formed. It can be formed by etching away.
【００１１】これらの基板を重ねて積層接着するには、
基板の間に、例えば、ガラス布に熱硬化性樹脂を含浸
し、加熱・乾燥して、半硬化状にしたプリプレグや、ポ
リエチレンテレフタレートフィルム上に熱硬化性樹脂を
塗布し、加熱・乾燥してドライフィルム状にした、接着
シート１６をはさみ、加熱・加圧して積層一体化するな
どして行うことができる。In order to laminate and bond these substrates,
Between the substrates, for example, a glass cloth is impregnated with a thermosetting resin, heated and dried, and a semi-cured prepreg or a polyethylene terephthalate film is coated with the thermosetting resin, and heated and dried. It can be carried out by sandwiching the adhesive sheet 16 formed into a dry film, heating and pressing to laminate and integrate.
【００１２】銅箔の表面に形成する保護膜１３には、通
常配線板に用いている、めっきレジストと呼ばれる樹脂
層を形成することが好ましく、このようなめっきレジス
トは、エポキシ樹脂のような熱硬化性樹脂を主成分と
し、硬化剤、硬化促進剤を含む樹脂組成物を溶剤に混合
したインク様のものや、そのような溶液を、ポリエチレ
ンテレフタレートフィルムなどの離型性を有するフィル
ムの上に塗布し、加熱・乾燥して半硬化状にしたドライ
フィルム状のものを用いる。インク様の溶液は、スクリ
ーン印刷法によって印刷して必要な形状に保護膜を形成
することができる。ドライフィルム状のものは、通常
は、硬化剤が光照射によって硬化するものが主流で、被
めっき体にラミネートし、形成する形状に光を透過する
フォトマスクを重ねて光照射し、露光しなかった部分を
現像液で除去することによって保護膜１３を形成するこ
とができる。It is preferable that a resin layer called a plating resist, which is usually used for a wiring board, be formed on the protective film 13 formed on the surface of the copper foil. A curable resin as a main component, a curing agent, an ink-like composition obtained by mixing a resin composition containing a curing accelerator in a solvent, and such a solution, on a film having a releasing property such as a polyethylene terephthalate film. A dry film that has been applied, heated and dried to a semi-cured state is used. The ink-like solution can be printed by a screen printing method to form a protective film in a required shape. In the case of dry film, usually, a curing agent is cured by light irradiation in a mainstream, and is laminated on a body to be plated, and a photomask that transmits light in a shape to be formed is irradiated with light, and is not exposed. The protective film 13 can be formed by removing the portion with the developing solution.
【００１３】キャビティ内に露出した内部接続端子２１
の表面に接続を強化するためのめっき２２には、ニッケ
ル、金、はんだ、白金、パラジウムなどがあり、ワイヤ
ボンディングなどのためには、ニッケル下地めっきの上
に、金、あるいはパラジウム／金のめっきを行うことが
好ましい。このときのニッケル下地めっきの厚さは、１
μｍ以上であることが好ましく、これより薄いとニッケ
ルめっきによる硬度が不足し、ワイヤボンディング性が
低下する。上限は特にないが、２０μｍを越えるとめっ
き時間が長くなるがワイヤボンディング性はそれに比例
して向上するわけでなく、経済的でない。より好ましく
は、５μｍ以上である。その上に行う金めっきの厚さ
は、０．１μｍ以上であることが好ましく、これより薄
いとボンディングワイヤとの接続強度が不足し、ワイヤ
ボンディング性が低下する。上限は特にないが、２μｍ
を越えるとめっき時間が長くなるがワイヤボンディング
性はそれに比例して向上するわけでなく、経済的でな
い。より好ましくは、０．５μｍ以上である。さらに
は、ニッケル下地めっきの上に、パラジウムめっきを行
った後に、金めっきを行うとワイヤボンディンブした接
続箇所の接続信頼性を高めることができ好ましい。この
ときのそれぞれのめっきの厚さは、合計で０．１μｍ以
上であることが好ましく、より好ましくは０．５μｍ以
上である。理由は、金めっきだけの場合と同じであり、
上限も、同様に２μｍを越えると経済的でない。この接
続を強化するためのめっき２２は、無電解めっきでも、
電解めっきでも行うことができ、このような無電解めっ
きは、めっきする金属のイオン源と、錯化剤、還元剤、
ｐＨ調整剤、安定性を改善する添加剤などから構成され
ている。めっきに先だって、被めっき体にパラジウムな
どのめっき用触媒を付与し、続いて、上記のような無電
解めっき液に浸漬することによって行うことができる。
さらに、ニッケル下地めっきを行った表面に、金、ある
いはパラジウム／金めっきを行うときには、下地めっき
のニッケルがめっき用触媒の働きをするので、めっき用
触媒を不要する必要はない。電解めっきの場合には、内
部接続端子２１と接続された電極用リードを設け、めっ
きした後の工程で、これを切断する工程を設けなければ
ならない。The internal connection terminal 21 exposed in the cavity
There are nickel, gold, solder, platinum, palladium, etc. in the plating 22 for strengthening the connection on the surface of the substrate. For wire bonding, gold or palladium / gold plating on a nickel base plating Is preferably performed. At this time, the thickness of the nickel base plating is 1
The thickness is preferably not less than μm, and if it is thinner than this, hardness by nickel plating is insufficient, and wire bonding property is reduced. There is no particular upper limit, but if it exceeds 20 μm, the plating time will be prolonged, but the wire bonding property will not be improved in proportion thereto and it is not economical. More preferably, it is 5 μm or more. The thickness of the gold plating to be performed thereon is preferably 0.1 μm or more. If the thickness is less than 0.1 μm, the connection strength with the bonding wire is insufficient, and the wire bonding property is reduced. There is no upper limit, but 2 μm
Exceeding the plating time increases the plating time, but does not improve the wire bonding property in proportion thereto, and is not economical. More preferably, it is 0.5 μm or more. Further, it is preferable that gold plating be performed after palladium plating is performed on the nickel base plating because the connection reliability of the connection portion bonded by wire bonding can be improved. At this time, the total thickness of each plating is preferably 0.1 μm or more, more preferably 0.5 μm or more. The reason is the same as for gold plating alone,
Similarly, if the upper limit exceeds 2 μm, it is not economical. The plating 22 for strengthening this connection can be formed by electroless plating,
Electroless plating can also be performed, and such electroless plating is performed by using an ion source of a metal to be plated, a complexing agent, a reducing agent,
It is composed of a pH adjuster, additives for improving stability, and the like. Prior to the plating, a plating catalyst such as palladium is applied to the object to be plated, and subsequently, the object is immersed in an electroless plating solution as described above.
Furthermore, when gold or palladium / gold plating is performed on the surface on which the nickel base plating has been performed, the nickel for the base plating acts as a plating catalyst, so that it is not necessary to use a plating catalyst. In the case of electrolytic plating, an electrode lead connected to the internal connection terminal 21 must be provided, and a step of cutting the electrode lead must be provided after plating.
【００１４】銅箔１５の表面に形成した保護膜１３を除
去するには、メチルエチルケトンなどのような溶剤に浸
漬する方法や、水酸化ナトリウムの水溶液のようなアル
カリ性の水溶液をスプレー噴霧して除去することができ
る。In order to remove the protective film 13 formed on the surface of the copper foil 15, a method of dipping in a solvent such as methyl ethyl ketone or an alkaline aqueous solution such as an aqueous solution of sodium hydroxide is sprayed and removed. be able to.
【００１５】スルーホール３１となる穴３０をあけるに
は、ドリルを用い、予め登録した穴径や位置によって、
ドリルの直径を選択し、指定された位置までドリルヘッ
ドを移動し、その位置でドリルを回転させながらドリル
ヘッドを降下させる、数値制御されたドリルマシンで行
うことが好ましい。To drill a hole 30 to be a through hole 31, a drill is used, and a hole diameter and a position registered in advance are used.
It is preferably done with a numerically controlled drill machine that selects the diameter of the drill, moves the drill head to a specified position, and lowers the drill head while rotating the drill at that position.
【００１６】穴３０の内壁を金属化するには、無電解め
っきあるいは、無電解めっきと電解めっきで行うことが
好ましく、特に銅めっきが接続抵抗が小さく経済的であ
ることからより好ましい。このような無電解めっきは、
めっきする金属のイオン源と、錯化剤、還元剤、ｐＨ調
整剤、安定性を改善する添加剤などから構成されてい
る。めっきに先だって、被めっき体にパラジウムなどの
めっき用触媒を付与し、続いて、上記のような無電解め
っき液に浸漬することによって行うことができる。この
無電解めっきは、厚さ１〜２５μｍの範囲で行うことが
好ましく、厚さが１μｍ未満であると、わずかのめっき
厚さのばらつきで導体抵抗が高くなりやすく好ましくな
い。この厚さが２５μｍを越えても特性上では特に問題
とならないが、無電解めっきそのものが析出速度が低い
ことから、長時間を要し、経済的でない。厚さを必要と
する場合には、無電解めっきで電流が流れる程度に薄
く、例えば、０．１〜２μｍ程度に析出させ、その上に
電解めっきを用いて行うのが効率的である。この電解め
っきには、硫酸浴、ピロリン酸浴、ワット浴など、通常
の配線板に用いる電解めっき方法を用いることができ
る。In order to metalize the inner wall of the hole 30, it is preferable to perform electroless plating or electroless plating and electrolytic plating. Copper plating is more preferable because it has low connection resistance and is economical. Such electroless plating is
It is composed of an ion source for the metal to be plated, a complexing agent, a reducing agent, a pH adjuster, and an additive for improving stability. Prior to the plating, a plating catalyst such as palladium is applied to the object to be plated, and subsequently, the object is immersed in an electroless plating solution as described above. This electroless plating is preferably performed in a thickness range of 1 to 25 μm, and if the thickness is less than 1 μm, a slight variation in plating thickness tends to increase conductor resistance, which is not preferable. Even if the thickness exceeds 25 μm, there is no particular problem in characteristics, but since the deposition rate of electroless plating itself is low, it takes a long time and is not economical. When a thickness is required, it is efficient to deposit by electroless plating thin enough to allow a current to flow, for example, to a thickness of about 0.1 to 2 μm, and then to perform electroplating thereon. For this electrolytic plating, an electrolytic plating method used for ordinary wiring boards, such as a sulfuric acid bath, a pyrophosphoric acid bath, and a Watts bath, can be used.
【００１７】この穴３０の内壁を金属化するときに、同
時にキャビティ内部に露出している内層回路の表面も金
属化され、接続の強化のためのめっき２２の上にも、そ
のめっき２２を行っていない箇所にも金属が析出され
る。When the inner wall of the hole 30 is metallized, the surface of the inner layer circuit exposed inside the cavity is also metallized at the same time, and the plating 22 is applied on the plating 22 for strengthening the connection. The metal is also deposited at the places where it is not present.
【００１８】銅箔１５の不要な箇所をエッチング除去し
て外層回路２６を形成するには、上述のめっきレジスト
と同様の組成物に、エッチング液に対する耐薬品性を向
上させる添加剤を用いるか組成物を調整した樹脂組成物
の溶液、あるいはドライフィルム状のエッチングレジス
ト材料を用い、スクリーン印刷やフォト法によってエッ
チングレジストを形成し、塩化第二銅溶液などのような
エッチング液をスプレー噴霧することにより、エッチン
グレジストを形成しなかった箇所の銅箔１２を選択的に
除去することによって行う。このときに、上述の接続を
強化するためのめっき２２は、エッチング除去のときの
ストッパーとして働き、内部接続端子２１はエッチング
液から保護される。そして、そのめっき２２を電解めっ
きによって行ったときに用いた、電極用のリードにはめ
っきされていないので、エッチング除去して、内部接続
端子２１を電極用リードから切断することができる。こ
の銅箔１５の不要な箇所をエッチング除去するときに、
キャビティ内の不要な金属化部分もエッチング除去する
ことができ、上述した、穴３０の内壁を金属化するとき
に、同時にキャビティ内部に露出している内層回路の表
面を金属化する工程の後に、上記の工程のエッチングレ
ジストを形成するときに、同様に、キャビティ内に露出
した必要とする内層回路の箇所にもエッチングレジスト
を形成しておき、上記の工程の不要な銅箔１５をエッチ
ング除去するときに、同時に、不要な箇所の内層回路の
部分をエッチング除去することができる。このようにし
て、図１（ｆ）に示すような、放熱を行うための金属層
１７も形成することができる。In order to form the outer layer circuit 26 by removing unnecessary portions of the copper foil 15 by etching, an additive for improving the chemical resistance to an etching solution is used in the same composition as the plating resist described above. By using a solution of a resin composition prepared as a product or an etching resist material in the form of a dry film, forming an etching resist by screen printing or a photo method, and spraying an etching solution such as a cupric chloride solution by spraying. This is performed by selectively removing the copper foil 12 at a place where the etching resist is not formed. At this time, the plating 22 for strengthening the connection described above functions as a stopper at the time of etching removal, and the internal connection terminal 21 is protected from the etching solution. Since the electrode lead used when the plating 22 is performed by electrolytic plating is not plated, the internal connection terminal 21 can be cut off from the electrode lead by etching away. When unnecessary portions of the copper foil 15 are removed by etching,
Unnecessary metallized portions in the cavity can also be etched away, and after the above-described step of metallizing the inner wall of the hole 30 and simultaneously metallizing the surface of the inner layer circuit exposed inside the cavity, Similarly, when forming the etching resist in the above step, an etching resist is also formed in the required portion of the inner layer circuit exposed in the cavity, and the unnecessary copper foil 15 in the above step is removed by etching. At the same time, unnecessary portions of the inner circuit can be removed by etching at the same time. In this manner, a metal layer 17 for heat dissipation as shown in FIG. 1F can be formed.
【００１９】外層回路２６に、他の基板との接続を行う
外部接続端子を形成することができ、その外部接続端子
の形状が残るようにエッチングレジストを形成すればよ
い。外部接続端子を形成した後に、その表面に接続を強
化する金属を形成することもでき、この金属は、内部接
続端子１２の表面に行う接続を強化するめっき２２と同
様に行うことができる。このときのニッケル下地めっき
の厚さは、１μｍ以上であることが好ましく、これより
薄いとニッケルめっきによる硬度が不足し、ワイヤボン
ディング性が低下する。上限は特にないが、２０μｍを
越えるとめっき時間が長くなるがワイヤボンディング性
はそれに比例して向上するわけでなく、経済的でない。
より好ましくは、５μｍ以上である。その上に行う金め
っきの厚さは、０．１μｍ以上であることが好ましく、
これより薄いとはんだボールとの接続強度が不足する。
上限は特にないが、２μｍを越えるとめっき時間が長く
なるがはんだボールとの接続強度がそれに比例して向上
するわけでなく、経済的でない。より好ましくは、０．
５μｍ以上である。さらには、ニッケル下地めっきの上
に、パラジウムめっきを行った後に、金めっきを行うと
はんだボールとの接続信頼性を高めることができ好まし
い。このときのそれぞれのめっきの厚さは、合計で０．
１μｍ以上であることが好ましく、より好ましくは０．
５μｍ以上である。理由は、金めっきだけの場合と同じ
であり、上限も、同様に２μｍを越えると経済的でな
い。External connection terminals for connection to another substrate can be formed in the outer layer circuit 26, and an etching resist may be formed so that the shape of the external connection terminals remains. After the external connection terminals are formed, a metal that enhances the connection can be formed on the surface of the external connection terminal. This metal can be formed similarly to the plating 22 that enhances the connection on the surface of the internal connection terminal 12. At this time, the thickness of the nickel base plating is preferably 1 μm or more. If the thickness is smaller than this, the hardness due to the nickel plating is insufficient, and the wire bonding property is reduced. There is no particular upper limit, but if it exceeds 20 μm, the plating time will be prolonged, but the wire bonding property will not be improved in proportion thereto and it is not economical.
More preferably, it is 5 μm or more. The thickness of the gold plating performed thereon is preferably 0.1 μm or more,
If the thickness is smaller than this, the connection strength with the solder ball is insufficient.
There is no particular upper limit, but if it exceeds 2 μm, the plating time will be prolonged, but the connection strength with the solder ball will not be improved in proportion thereto, and it is not economical. More preferably, 0.
5 μm or more. Further, it is preferable that gold plating is performed after palladium plating is performed on the nickel base plating because the connection reliability with the solder ball can be improved. At this time, the thickness of each plating is 0.1 mm in total.
It is preferably at least 1 μm, more preferably 0.1 μm.
5 μm or more. The reason is the same as in the case of only gold plating. Similarly, if the upper limit exceeds 2 μm, it is not economical.
【００２０】また、上記の方法で製造された半導体パッ
ケージ用基板のキャビティ部に半導体チップを搭載すれ
ば、半導体パッケージを製造することができ、さらに
は、キャビティ内の半導体チップを、封止樹脂で封止す
ることもできる。A semiconductor package can be manufactured by mounting a semiconductor chip in the cavity of the semiconductor package substrate manufactured by the above method. Further, the semiconductor chip in the cavity is sealed with a sealing resin. It can also be sealed.
【００２１】[0021]
【実施例】図２（ａ）に示すように、両面に１２μｍの
銅箔１５ａを貼り合わせた、厚さ０．４ｍｍのガラス布
基材エポキシ樹脂銅張り積層板であるＭＣＬ−Ｅ−６７
９（日立化成工業株式会社製、商品名）にキャビティと
なる開口部３ａを、ルータドリル機であるＮＲ−２Ｃ１
８（日立精工業株式会社製、商品名）によりあけ、不要
な片面の銅箔１５ａをエッチング除去し、開口部を有す
る基板１０ａを準備した。両面に１２μｍの銅箔１５ｂ
を貼り合わせた、厚さ０．１ｍｍのガラス布基材エポキ
シ樹脂銅張り積層板であるＭＣＬ−Ｅ−６７９（日立化
成工業株式会社製、商品名）にキャビティとなる開口部
を、ルータドリル機であるＮＲ−２Ｃ１８（日立精工業
株式会社製、商品名）によりあけ、無電解銅めっきを行
って両面の銅箔１５ｂを電気的に接続し、開口部の壁に
導体を形成し、不要な箇所の銅をエッチング除去して、
内層回路２３ｂと内部接続端子２１ｂを有する基板２０
ｂを準備した。このときの開口部は、基板１０ａの開口
部とほぼ同じ大きさに形成した。また、全ての内部接続
端子２１ｂを接続するめっき用リード２４ｂも形成し
た。同様にして、両面に１２μｍの銅箔を貼り合わせ
た、厚さ０．１ｍｍのガラス布基材エポキシ樹脂銅張り
積層板であるＭＣＬ−Ｅ−６７９（日立化成工業株式会
社製、商品名）にキャビティとなる開口部を、ルータド
リル機であるＮＲ−２Ｃ１８（日立精工業株式会社製、
商品名）によりあけ、無電解銅めっきを行って両面の銅
箔を電気的に接続し、開口部の壁に導体を形成し、不要
な箇所の銅をエッチング除去して、内層回路２３ｃと内
部接続端子２１ｃを有する基板２０ｃを準備した。この
ときの開口部は、基板２０ｂの開口部よりも大きく形成
した。また、全ての内部接続端子２１ｃを接続するめっ
き用リード２４ｃも形成した。同様にして、両面に１２
μｍの銅箔１５ｄを貼り合わせた、厚さ０．４ｍｍのガ
ラス布基材エポキシ樹脂銅張り積層板であるＭＣＬ−Ｅ
−６７９（日立化成工業株式会社製、商品名）にキャビ
ティとなる開口部を、ルータドリル機であるＮＲ−２Ｃ
１８（日立精工業株式会社製、商品名）によりあけ、不
要な片面の銅箔１５ｄをエッチング除去し、開口部を有
する基板１０ｄを準備した。このときの開口部は、基板
２０ｃの開口部より大きく形成した。接着シートとし
て、基板１０ａと基板２０ｂの間、及び、基板２０ｃと
基板１０ｄの間に挟む接着シート５１ａ，５１ｃには、
厚さ２５μｍのエポキシ系ドライフィルム状の接着シー
トを用い、基板２０ｂと基板２０ｃとの間に挟む接着シ
ート５２ｂには、絶縁性を高めるために、厚さ０．１ｍ
ｍのガラス布基材エポキシ樹脂プリプレグであるＧＥＡ
−６７９（日立化成工業株式会社製、商品名）を用い
た。そしてこれらの接着シート５１ａ，５１ｃ，５２ｂ
には、それぞれの基板に設けた開口部に合わせて、開口
部を打ち抜き金型で形成した。これらの材料を、図２
（ａ）に示すように重ね、プレス機により、１８０℃の
温度で、圧力を３ＭＰａとし、９０分間、加熱・加圧し
て積層一体化した。このように積層一体化した多層板の
めっきレジスト２８として、図２（ｂ）に示すように、
厚さ５０μｍのめっきレジスト用ドライフィルムである
Ｈ−Ｗ４４０（日立化成工業株式会社製、商品名）をラ
ミネートした後、ザグリ加工で内部接続端子２１ｂ、２
１ｃを露出させて、接続を強化するためのめっき２２と
して、拡大図Ａに示すように、ニッケルめっき２２１と
金めっき２２２を続けて行った。このときのニッケルめ
っき２２１は、ワット浴の無光沢ニッケル浴で、電流密
度１．３Ａ／ｄｍ2、金めっき２２２は、テンテレック
ス４０１液（日本ＥＥＪＡ社製、商品名）、０．４Ａ／
ｄｍ2の条件で行った。このときのニッケルめっき２２
１の厚さは２μｍ、金めっき２２２の厚さは０．１μｍ
であった。図２（ｃ）に示すように、前記ドライフィル
ムのめっきレジストを、メチルエチルケトンに浸漬して
剥離除去した後、所定の場所にＮＣドリル機により、ス
ルーホール３１となる穴をあけ、無電解銅めっき液であ
るＬ５９（日立化成工業株式会社製、商品名）に浸漬
し、厚さ２５μｍに銅５３を析出させた。更に、その銅
５３の表面に、外層回路２６の形状にエッチングレジス
トを形成し、エッチング液としてアルカリ系エッチング
液を用いて、エッチングレジストから露出した銅５３を
エッチング除去して、外層回路２６を形成した。このと
きに、キャビティの内側にはエッチングレジストを形成
しなかったので、内部接続端子２１ｂ、２１ｃが露出
し、めっきリード２４ｂ、２４ｃはエッチング除去され
た。その後、ソルダーレジスト用ドライフィルムである
ＳＲ−７０００（日立化成工業株式会社製、商品名）を
ラミネートし、図２（ｄ）に示すように、外部接続端子
の箇所を除いてソルダーレジスト２７を形成し、更に、
めっきレジスト用ドライフィルムであるＨ−Ｋ６５０
（日立化成工業株式会社製、商品名）をラミネートし、
キャビティ部を保護するように、めっきレジスト２８を
形成し、外部接続端子に、接続を強化するためのめっき
２２として、ニッケルめっきと金めっきを続けて行っ
た。このときのニッケルめっきは、ワット浴の無光沢ニ
ッケル浴で、電流密度１．３Ａ／ｄｍ2、金めっきは、
テンテレックス４０１液（日本ＥＥＪＡ社製、商品
名）、０．４Ａ／ｄｍ2であった。このときのニッケル
めっきの厚さは２μｍ、金めっきの厚さは０．１μｍで
あった。その後、ヒートシンク４１を接着し、外形加工
により所定のサイズに個片加工した。次に、図２（ｅ）
に示すように、裏面にダイボンディングフィルムを貼り
合わせた半導体チップ６を、ヒートシンク４１の上に接
着・固定し、半導体チップ６の端子と内部接続端子２１
をボンディングワイヤ７で接続した後、封止樹脂８で封
止した。As shown in FIG. 2 (a), MCL-E-67 is a 0.4 mm-thick glass cloth-based epoxy resin copper-clad laminate having a 12 μm copper foil 15a bonded to both sides.
9 (manufactured by Hitachi Chemical Co., Ltd., trade name), the opening 3a to be a cavity is inserted into a NR-2C1 router drill machine.
8 (manufactured by Hitachi Seimitsu Co., Ltd., trade name), and unnecessary one side copper foil 15a was removed by etching to prepare substrate 10a having an opening. 12μm copper foil 15b on both sides
An opening part to be a cavity is formed on a 0.1 mm thick glass cloth base epoxy resin copper-clad laminate MCL-E-679 (manufactured by Hitachi Chemical Co., Ltd.) with a router drill machine. NR-2C18 (trade name, manufactured by Hitachi Seimitsu Industry Co., Ltd.), electroless copper plating is performed to electrically connect the copper foils 15b on both sides, and a conductor is formed on the wall of the opening, which is unnecessary. By etching away the copper
Substrate 20 having inner layer circuit 23b and internal connection terminal 21b
b was prepared. The opening at this time was formed to have substantially the same size as the opening of the substrate 10a. Further, plating leads 24b for connecting all the internal connection terminals 21b were also formed. Similarly, a MCL-E-679 (trade name, manufactured by Hitachi Chemical Co., Ltd.), a 0.1 mm-thick glass-cloth-based epoxy resin copper-clad laminate having 12 μm copper foil laminated on both sides, was used. The opening to be a cavity is placed in a router drill machine NR-2C18 (Hitachi Seimitsu Co., Ltd.
Opening by electroless copper plating, electrically connecting the copper foil on both sides, forming a conductor on the wall of the opening, etching away unnecessary copper, and removing the inner circuit 23c A substrate 20c having a connection terminal 21c was prepared. The opening at this time was formed larger than the opening of the substrate 20b. Further, plating leads 24c for connecting all the internal connection terminals 21c were also formed. Similarly, 12 on both sides
MCL-E, a 0.4 mm-thick glass-cloth-based epoxy resin copper-clad laminate with 15 μm copper foil 15d
-679 (trade name, manufactured by Hitachi Chemical Co., Ltd.), the opening to be a cavity, NR-2C router drill machine
18 (manufactured by Hitachi Seimitsu Co., Ltd., trade name), and unnecessary copper foil 15d on one side was removed by etching to prepare a substrate 10d having an opening. The opening at this time was formed larger than the opening of the substrate 20c. As adhesive sheets, adhesive sheets 51a and 51c sandwiched between the substrate 10a and the substrate 20b and between the substrate 20c and the substrate 10d include:
An epoxy-based dry film adhesive sheet having a thickness of 25 μm was used, and an adhesive sheet 52b sandwiched between the substrate 20b and the substrate 20c was provided with a thickness of 0.1 m to enhance insulation.
GEA which is a glass cloth based epoxy resin prepreg
-679 (trade name, manufactured by Hitachi Chemical Co., Ltd.) was used. And these adhesive sheets 51a, 51c, 52b
The openings were formed by punching dies in accordance with the openings provided in the respective substrates. These materials are shown in FIG.
As shown in (a), the layers were stacked and integrated by pressing and heating at a temperature of 180 ° C. and a pressure of 3 MPa for 90 minutes using a press machine. As shown in FIG. 2 (b), the plating resist 28 of the multilayer board thus laminated and integrated is as follows.
After laminating H-W440 (trade name, manufactured by Hitachi Chemical Co., Ltd.) which is a dry film for plating resist having a thickness of 50 μm, the internal connection terminals 21b, 2
As plating 22 for exposing 1c and strengthening the connection, nickel plating 221 and gold plating 222 were successively performed as shown in enlarged view A. The nickel plating 221 at this time is a matte nickel bath of a watt bath, and has a current density of 1.3 A / dm 2 , and the gold plating 222 is a tenterex 401 solution (trade name, manufactured by EEJA Japan, Inc.), 0.4 A /
dm 2 . Nickel plating 22 at this time
The thickness of 1 is 2 μm, and the thickness of gold plating 222 is 0.1 μm
Met. As shown in FIG. 2C, after the plating resist of the dry film is immersed in methyl ethyl ketone and peeled off, a hole to be a through hole 31 is made in a predetermined place by an NC drilling machine, and electroless copper plating is performed. It was immersed in a liquid L59 (trade name, manufactured by Hitachi Chemical Co., Ltd.) to precipitate copper 53 to a thickness of 25 μm. Further, an etching resist is formed on the surface of the copper 53 in the shape of the outer circuit 26, and the copper 53 exposed from the etching resist is removed by etching using an alkaline etching solution as an etching solution to form the outer circuit 26. did. At this time, since no etching resist was formed inside the cavity, the internal connection terminals 21b and 21c were exposed, and the plating leads 24b and 24c were removed by etching. Thereafter, SR-7000 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a dry film for a solder resist, is laminated, and as shown in FIG. 2D, a solder resist 27 is formed except for the locations of external connection terminals. And then
H-K650 which is a dry film for plating resist
(Made by Hitachi Chemical Co., Ltd., trade name)
A plating resist 28 was formed so as to protect the cavity, and nickel plating and gold plating were successively performed on the external connection terminals as the plating 22 for strengthening the connection. The nickel plating at this time is a matte nickel bath of a watt bath, the current density is 1.3 A / dm 2 , and the gold plating is
Tenterex 401 liquid (trade name, manufactured by EEJA Japan) was 0.4 A / dm 2 . At this time, the thickness of the nickel plating was 2 μm, and the thickness of the gold plating was 0.1 μm. Thereafter, the heat sink 41 was bonded, and individual pieces were processed into a predetermined size by external processing. Next, FIG.
As shown in FIG. 7, a semiconductor chip 6 having a rear surface bonded with a die bonding film is adhered and fixed on a heat sink 41, and the terminals of the semiconductor chip 6 and the internal connection terminals 21 are formed.
Was connected with a bonding wire 7 and then sealed with a sealing resin 8.
【００２２】本実施例の効果として、最外層の基板を窓
加工して積層した事により、キャビティ部の蓋を加工し
キャビティを露出させないようにした事により、加工位
置精度が向上した。更に、キャビティ部の先にニッケル
金めっきを行い、永久ソルダーレジスト形成後外層パッ
ド部のニッケル金めっきを行うことにより、金めっき厚
さがキャビティ部を厚く、外層パッド部を薄く設定する
ことができる事によい、外部接続の信頼性が向上するこ
とができた。The effect of this embodiment is that the outermost layer substrate is window-processed and laminated, so that the cavity lid is processed so that the cavity is not exposed, thereby improving the processing position accuracy. Further, by performing nickel gold plating on the tip of the cavity portion and performing nickel gold plating on the outer layer pad portion after forming the permanent solder resist, the gold plating thickness can be set to be thicker for the cavity portion and thinner for the outer layer pad portion. Good thing, the reliability of the external connection could be improved.
【００２３】[0023]
【発明の効果】以上に説明したとおり、本発明によっ
て、小型化にすぐれ、外層回路にも内部接続端子と同じ
種類の、接続を強化するめっきを行う場合でも、めっき
の膜厚のばらつきが少なく、内部接続端子のワイヤボン
ディング性に優れ、かつ外部接続端子の接続信頼性に優
れた半導体パッケージ用基板の製造方法とその方法を用
いた半導体パッケージの製造方法及びこれらの方法を用
いた半導体パッケージ用基板と半導体パッケージを提供
することができた。As described above, according to the present invention, even when the outer layer circuit is plated with the same type as the internal connection terminal, the variation in plating film thickness is small even when the outer layer circuit is plated with the same type as the internal connection terminal. Patent application title: Method of manufacturing semiconductor package substrate excellent in wire bonding property of internal connection terminal and excellent in connection reliability of external connection terminal, method of manufacturing semiconductor package using the method, and method of manufacturing semiconductor package using these methods Substrate and semiconductor package could be provided.
【図１】（ａ）〜（ｄ）は、それぞれ、本発明の原理を
説明するための各工程での断面図であり、（ｅ）は、そ
の実施態様の一例を示す断面図である。FIGS. 1A to 1D are cross-sectional views in each step for explaining the principle of the present invention, and FIG. 1E is a cross-sectional view showing an example of the embodiment.
【図２】（ａ）〜（ｋ）は、それぞれ本発明の一実施例
を示す、各工程における断面図である。2 (a) to 2 (k) are cross-sectional views in each step showing one embodiment of the present invention.
【図３】（ａ）〜（ｅ）は、それぞれ、本発明の他の態
様を示す断面図である。FIGS. 3A to 3E are cross-sectional views showing other embodiments of the present invention.
【図４】（ａ）〜（ｆ）は、それぞれ、従来例を示す、
各工程での断面図である。FIGS. 4A to 4F each show a conventional example.
It is sectional drawing in each process.
６．半導体チップ ７．ボンディングワイヤ ８．封止樹脂 １０，１０ａ，１０ｄ，１１０．開口部を有する基板 １３．保護膜 １５，１５ａ，１５ｄ．銅箔 １６．放熱を行うための金属層 １２０，２０，２０ｂ，２０ｃ．内部接続端子を有する
基板 ２１，２１ｂ，２１ｃ．内部接続端子 ２２．接続を強化するためのめっき ２３ｂ，２３ｃ．内層回路 ２４ｂ，２４ｃ．めっき用リード ２６．外層回路 ２７．ソルダーレジスト ２８．めっきレジスト ２９．外部接続端子 ３０，１３０．スルーホール ３１，１３１．スルーホールとなる穴 ４１．ヒートシンク １００．内部接続端子を保護するための基板 ２０１．下の基板 ２０２．上の基板 １３１．スルーホール １２６．外層回路 １２２．接続を強化するためのめっき6. Semiconductor chip 7. Bonding wire 8. Sealing resin 10, 10a, 10d, 110. Substrate having opening 13. Protective film 15, 15a, 15d. Copper foil 16. Metal layers for heat dissipation 120, 20, 20b, 20c. Substrate having internal connection terminals 21, 21b, 21c. Internal connection terminal 22. Plating to strengthen connections 23b, 23c. Inner layer circuit 24b, 24c. Lead for plating 26. Outer layer circuit 27. Solder resist 28. Plating resist 29. External connection terminals 30, 130. Through holes 31, 131. Hole to be a through hole 41. Heat sink 100. Board for protecting internal connection terminals 201. Lower substrate 202. Upper substrate 131. Through hole 126. Outer layer circuit 122. Plating to strengthen connections
Claims (14)
ィを有し、そのキャビティ内に半導体チップと接続する
内部接続端子を有する半導体パッケージ用基板の製造方
法において、キャビティとなる開口部を有すると共に銅
箔を有する基板を、キャビティの内側となる箇所に少な
くとも半導体チップと接続する内部接続端子を有する基
板の上に重ねて積層接着し、銅箔の表面に保護膜を形成
し、キャビティ内に露出した内部接続端子の表面に接続
を強化するためのめっきを行い、銅箔の表面の保護膜を
除去し、スルーホールとなる穴をあけ、穴内壁とキャビ
ティ内壁とを金属化し、銅箔の不要な箇所と不要な金属
をエッチング除去して、内部接続端子を露出すると共に
外層回路を形成する工程を有する半導体パッケージ用基
板の製造方法。1. A method of manufacturing a semiconductor package substrate having a cavity at a position where a semiconductor chip is mounted, and having an internal connection terminal connected to the semiconductor chip in the cavity. A substrate having a foil was overlaid and bonded on a substrate having at least an internal connection terminal connected to a semiconductor chip at a location inside the cavity, a protective film was formed on the surface of the copper foil, and exposed inside the cavity. The surface of the internal connection terminal is plated to strengthen the connection, the protective film on the surface of the copper foil is removed, a hole is formed as a through hole, the inner wall of the hole and the inner wall of the cavity are metallized, and unnecessary copper foil is used. A method for manufacturing a substrate for a semiconductor package, comprising a step of exposing internal connection terminals and forming an outer layer circuit by removing portions and unnecessary metal by etching.
ィを有し、そのキャビティ内に半導体チップと接続する
内部接続端子を有する半導体パッケージ用基板の製造方
法において、キャビティとなる開口部を有する基板を、
キャビティの内側となる箇所に少なくとも半導体チップ
と接続する内部接続端子を有すると共に銅箔を有する基
板の上に重ねて積層接着し、銅箔の表面に保護膜を形成
し、キャビティ内に露出した内部接続端子の表面に接続
を強化するためのめっきを行い、銅箔の表面の保護膜を
除去し、スルーホールとなる穴をあけ、穴内壁とキャビ
ティ内壁とを金属化し、銅箔の不要な箇所と不要な金属
をエッチング除去して、内部接続端子を露出すると共に
外層回路を形成する工程を有する半導体パッケージ用基
板の製造方法。2. A method of manufacturing a semiconductor package substrate having a cavity at a position where a semiconductor chip is mounted and having an internal connection terminal connected to the semiconductor chip in the cavity. ,
It has an internal connection terminal connected to at least a semiconductor chip at a location inside the cavity and overlaps and laminates on a substrate having copper foil, forms a protective film on the surface of the copper foil, and exposes the inside exposed inside the cavity. Plating is performed on the surface of the connection terminal to strengthen the connection, the protective film on the surface of the copper foil is removed, holes are formed as through holes, and the inner wall of the hole and the inner wall of the cavity are metallized. And a step of exposing unnecessary internal metals to expose internal connection terminals and forming an outer layer circuit.
ィを有し、そのキャビティ内に半導体チップと接続する
内部接続端子を有する半導体パッケージ用基板の製造方
法において、キャビティとなる開口部を有すると共に銅
箔を有する基板を、キャビティの内側となる箇所に少な
くとも半導体チップと接続する内部接続端子を有すると
共に銅箔を有する基板の上に重ねて積層接着し、銅箔の
表面に保護膜を形成し、キャビティ内に露出した内部接
続端子の表面に接続を強化するためのめっきを行い、銅
箔の表面に保護膜を形成し、キャビティ内に露出した内
部接続端子の表面に接続を強化するためのめっきを行
い、銅箔の表面の保護膜を除去し、スルーホールとなる
穴をあけ、穴内壁とキャビティ内壁とを金属化し、銅箔
の不要な箇所と不要な金属をエッチング除去して、内部
接続端子を露出すると共に外層回路を形成する工程を有
する半導体パッケージ用基板の製造方法。3. A method of manufacturing a semiconductor package substrate having a cavity at a position where a semiconductor chip is mounted and having an internal connection terminal connected to the semiconductor chip in the cavity. A substrate having a foil is laminated and adhered on a substrate having a copper foil while having internal connection terminals connected to at least a semiconductor chip at a location inside the cavity, and a protective film is formed on the surface of the copper foil, Plating for strengthening the connection on the surface of the internal connection terminal exposed in the cavity, forming a protective film on the surface of the copper foil, and plating on the surface of the internal connection terminal exposed in the cavity for strengthening the connection To remove the protective film on the surface of the copper foil, make a hole to be a through hole, and metalize the inner wall of the hole and the inner wall of the cavity. The metal is etched away, a manufacturing method of a substrate for a semiconductor package having a step of forming an outer layer circuit with exposing the internal connecting terminal.
半導体チップと接続する内部接続端子を有する基板が、
複数枚であって、下の基板の内部接続端子が露出するよ
うに、上の基板に開口部を設ける工程を有する請求項１
〜３に記載の半導体パッケージ用基板の製造方法。4. A substrate having an internal connection terminal connected to at least a semiconductor chip at a position inside a cavity,
2. The method according to claim 1, further comprising the step of providing an opening in the upper substrate so that the internal connection terminals of the lower substrate are exposed.
4. The method of manufacturing a substrate for a semiconductor package according to any one of items 1 to 3.
半導体チップと接続する内部接続端子を有する基板の裏
面に、半導体チップの放熱のためのヒートシンクを貼り
合わせる工程を有する請求項１〜４のうちいずれかに記
載の半導体パッケージ用基板の製造方法。5. The method according to claim 1, further comprising the step of attaching a heat sink for heat dissipation of the semiconductor chip to the back surface of the substrate having at least an internal connection terminal connected to the semiconductor chip at a position inside the cavity. 13. A method for manufacturing a substrate for a semiconductor package according to
搭載する箇所に直接ヒートシンクが露出するように構成
する工程を有する請求項５に記載の半導体パッケージ用
基板の製造方法。6. The method for manufacturing a substrate for a semiconductor package according to claim 5, further comprising the step of providing an opening in the substrate 20 so that the heat sink is directly exposed at a position where the semiconductor chip is mounted.
部に露出している内層回路の表面も金属化する請求項１
〜６のうちいずれかに記載の半導体パッケージ用基板の
製造方法。7. The inner wall of the hole is metallized, and the surface of the inner layer circuit exposed inside the cavity is also metallized.
7. The method of manufacturing a substrate for a semiconductor package according to any one of the above items.
きに、キャビティ内の不要な金属化部分もエッチング除
去する請求項１〜７のうちいずれかに記載の半導体パケ
ージ用基板の製造方法。8. The method of manufacturing a semiconductor package substrate according to claim 1, wherein when unnecessary portions of the copper foil are removed by etching, unnecessary metallized portions in the cavities are also removed by etching.
接続端子を有する請求項１〜８のうちいずれかに記載の
半導体パッケージ用基板。9. The substrate for a semiconductor package according to claim 1, wherein the outer layer circuit has an external connection terminal for connecting to another substrate.
に接続を強化する金属を形成する請求項９に記載の半導
体パッケージ用基板の製造方法。10. The method of manufacturing a semiconductor package substrate according to claim 9, wherein after forming the external connection terminal, a metal for strengthening the connection is formed on the surface of the external connection terminal.
方法により製造された半導体パッケージ用基板。11. A semiconductor package substrate manufactured by the method according to claim 1.
方法で製造された半導体パッケージ用基板のキャビティ
部に半導体チップを搭載する工程を有する半導体パッケ
ージの製造方法。12. A method of manufacturing a semiconductor package, comprising: mounting a semiconductor chip in a cavity of a semiconductor package substrate manufactured by the method according to claim 1.
脂で封止する工程を有する請求項１２に記載の半導体パ
ッケージの製造方法。13. The method of manufacturing a semiconductor package according to claim 12, further comprising a step of sealing the semiconductor chip in the cavity with a sealing resin.
り製造された半導体パッケージ。14. A semiconductor package manufactured by the method according to claim 12.
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|---|---|---|---|
| JP2000221615A JP4840628B2 (en) | 2000-07-24 | 2000-07-24 | Semiconductor package substrate manufacturing method, semiconductor package manufacturing method using the method, and semiconductor package substrate and semiconductor package using these methods |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000221615A JP4840628B2 (en) | 2000-07-24 | 2000-07-24 | Semiconductor package substrate manufacturing method, semiconductor package manufacturing method using the method, and semiconductor package substrate and semiconductor package using these methods |
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| Publication Number | Publication Date |
|---|---|
| JP2002043454A true JP2002043454A (en) | 2002-02-08 |
| JP4840628B2 JP4840628B2 (en) | 2011-12-21 |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004265956A (en) * | 2003-02-26 | 2004-09-24 | Ibiden Co Ltd | Multilayer printed wiring board |
| JP2004281849A (en) * | 2003-03-18 | 2004-10-07 | Sumitomo Metal Electronics Devices Inc | High heat radiation plastic package and its manufacturing method |
| US7462555B2 (en) | 2004-12-17 | 2008-12-09 | Samsung Electro-Mechanics Co., Ltd. | Ball grid array substrate having window and method of fabricating same |
| US7894203B2 (en) | 2003-02-26 | 2011-02-22 | Ibiden Co., Ltd. | Multilayer printed wiring board |
| KR101214357B1 (en) * | 2008-09-29 | 2012-12-20 | 히다치 가세고교 가부시끼가이샤 | Semiconductor element-mounting package substrate, and method for manufacturing package substrate |
| CN105338751A (en) * | 2014-08-12 | 2016-02-17 | 富葵精密组件(深圳)有限公司 | Circuit board and fabrication method thereof |
| CN113035794A (en) * | 2021-02-01 | 2021-06-25 | 珠海越亚半导体股份有限公司 | Chip packaging structure manufacturing method and chip packaging structure |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6175596A (en) * | 1984-09-20 | 1986-04-17 | イビデン株式会社 | Manufacture of through hole multilayer circuit board |
| JPH0637457A (en) * | 1992-07-15 | 1994-02-10 | Matsushita Electric Works Ltd | Manufacture of printed wiring board |
| JPH08181455A (en) * | 1994-10-27 | 1996-07-12 | Matsushita Electric Works Ltd | Manufacture of multilayer printed circuit board |
| JPH1013037A (en) * | 1996-06-19 | 1998-01-16 | Ibiden Co Ltd | Method for manufacturing multilayer printed wiring board for mounting ic |
| JPH10178122A (en) * | 1996-12-18 | 1998-06-30 | Ibiden Co Ltd | Ic mounting multilayer printed wiring board |
| JPH11163528A (en) * | 1997-11-21 | 1999-06-18 | Ibiden Co Ltd | Multilayer electronic component mounting board and its manufacture |
| JPH11176976A (en) * | 1997-12-08 | 1999-07-02 | Sumitomo Metal Smi Electron Devices Inc | Manufacture for electronic components package |
-
2000
- 2000-07-24 JP JP2000221615A patent/JP4840628B2/en not_active Expired - Lifetime
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6175596A (en) * | 1984-09-20 | 1986-04-17 | イビデン株式会社 | Manufacture of through hole multilayer circuit board |
| JPH0637457A (en) * | 1992-07-15 | 1994-02-10 | Matsushita Electric Works Ltd | Manufacture of printed wiring board |
| JPH08181455A (en) * | 1994-10-27 | 1996-07-12 | Matsushita Electric Works Ltd | Manufacture of multilayer printed circuit board |
| JPH1013037A (en) * | 1996-06-19 | 1998-01-16 | Ibiden Co Ltd | Method for manufacturing multilayer printed wiring board for mounting ic |
| JPH10178122A (en) * | 1996-12-18 | 1998-06-30 | Ibiden Co Ltd | Ic mounting multilayer printed wiring board |
| JPH11163528A (en) * | 1997-11-21 | 1999-06-18 | Ibiden Co Ltd | Multilayer electronic component mounting board and its manufacture |
| JPH11176976A (en) * | 1997-12-08 | 1999-07-02 | Sumitomo Metal Smi Electron Devices Inc | Manufacture for electronic components package |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004265956A (en) * | 2003-02-26 | 2004-09-24 | Ibiden Co Ltd | Multilayer printed wiring board |
| JP4493923B2 (en) * | 2003-02-26 | 2010-06-30 | イビデン株式会社 | Printed wiring board |
| US7894203B2 (en) | 2003-02-26 | 2011-02-22 | Ibiden Co., Ltd. | Multilayer printed wiring board |
| JP2004281849A (en) * | 2003-03-18 | 2004-10-07 | Sumitomo Metal Electronics Devices Inc | High heat radiation plastic package and its manufacturing method |
| US7462555B2 (en) | 2004-12-17 | 2008-12-09 | Samsung Electro-Mechanics Co., Ltd. | Ball grid array substrate having window and method of fabricating same |
| KR101214357B1 (en) * | 2008-09-29 | 2012-12-20 | 히다치 가세고교 가부시끼가이샤 | Semiconductor element-mounting package substrate, and method for manufacturing package substrate |
| CN105338751A (en) * | 2014-08-12 | 2016-02-17 | 富葵精密组件(深圳)有限公司 | Circuit board and fabrication method thereof |
| CN113035794A (en) * | 2021-02-01 | 2021-06-25 | 珠海越亚半导体股份有限公司 | Chip packaging structure manufacturing method and chip packaging structure |
| CN113035794B (en) * | 2021-02-01 | 2023-04-07 | 珠海越亚半导体股份有限公司 | Chip packaging structure manufacturing method and chip packaging structure |
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