JPS5692471A - Test device - Google Patents

Test device

Info

Publication number
JPS5692471A
JPS5692471A JP16901779A JP16901779A JPS5692471A JP S5692471 A JPS5692471 A JP S5692471A JP 16901779 A JP16901779 A JP 16901779A JP 16901779 A JP16901779 A JP 16901779A JP S5692471 A JPS5692471 A JP S5692471A
Authority
JP
Japan
Prior art keywords
cycles
memory
expected value
register group
stores
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16901779A
Other languages
Japanese (ja)
Inventor
Yasutaka Hirozawa
Takahiko Ogita
Yukio Nozoe
Tsune Morioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16901779A priority Critical patent/JPS5692471A/en
Publication of JPS5692471A publication Critical patent/JPS5692471A/en
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE: To decrease hardware of holding means and make constitution simple by holding only the expected value for a response output if the testing of said response output is necessary.
CONSTITUTION: The information necessary for checking is stored in a register group 4. In (n) cycles, a memory 25 makes operation of (n-3) cycles. In (n+1) cycles, the memory 25 makes operation of (n-2) cycles, and a testing circuit stores the expected value into the FF1 of a register group 4. In (n+2) cycles, the memory 25 makes operation of (n-1) cycles. The contents of the FF1 remain intact. In (n+3) cycles, the memory 25 makes write operation of n cycles and the testing circuit stores the contents of the FF1 of the register group 4 into an FF2 and the FF1 stores the new expected value. In (n+4) cycles, the memory 25 makes read operation of (n+1) cycles and a checking circuit 13 compares the output of the FF2 with the read data from the memory 4 and generates an error signal.
COPYRIGHT: (C)1981,JPO&Japio
JP16901779A 1979-12-25 1979-12-25 Test device Pending JPS5692471A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16901779A JPS5692471A (en) 1979-12-25 1979-12-25 Test device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16901779A JPS5692471A (en) 1979-12-25 1979-12-25 Test device

Publications (1)

Publication Number Publication Date
JPS5692471A true JPS5692471A (en) 1981-07-27

Family

ID=15878781

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16901779A Pending JPS5692471A (en) 1979-12-25 1979-12-25 Test device

Country Status (1)

Country Link
JP (1) JPS5692471A (en)

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