JPS5691446A - Forming of element segregation region of semiconductor integrated circuit - Google Patents

Forming of element segregation region of semiconductor integrated circuit

Info

Publication number
JPS5691446A
JPS5691446A JP16870079A JP16870079A JPS5691446A JP S5691446 A JPS5691446 A JP S5691446A JP 16870079 A JP16870079 A JP 16870079A JP 16870079 A JP16870079 A JP 16870079A JP S5691446 A JPS5691446 A JP S5691446A
Authority
JP
Japan
Prior art keywords
membrane
silicon nitride
silicon
oxidized
nitride membrane
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16870079A
Other languages
Japanese (ja)
Inventor
Yoshihiro Maeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP16870079A priority Critical patent/JPS5691446A/en
Publication of JPS5691446A publication Critical patent/JPS5691446A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To obtain an oxidized mask pattern less susceptible of cracks, by conducting anisotropic etching of silicon nitride membrane, provided on a silicon substrate, in fluorocarbon type gas. CONSTITUTION:An oxidized silicon membrane 2 and a silicon nitride membrane 3 are formed a silicon substrate 1, and a photoresist layer 4 of a prescribed pattern is attached to the membrane. When plasma etching is conducted in a gas containing helium composed mainly of Freon 116, the silicon nitride membrane 3 and the oxidized silicon membrane 2 are anisotropically etched in vertical direction when an etching method of this type is employed, lateral etching of the silicon nitride membrane 3 becomes less, and therefore, the silicon nitride membrane 3 become prevented from occurrence of cracks by stress even if a field oxidized membrane were to be formed in the subsequent oxidizing process.
JP16870079A 1979-12-25 1979-12-25 Forming of element segregation region of semiconductor integrated circuit Pending JPS5691446A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16870079A JPS5691446A (en) 1979-12-25 1979-12-25 Forming of element segregation region of semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16870079A JPS5691446A (en) 1979-12-25 1979-12-25 Forming of element segregation region of semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5691446A true JPS5691446A (en) 1981-07-24

Family

ID=15872830

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16870079A Pending JPS5691446A (en) 1979-12-25 1979-12-25 Forming of element segregation region of semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5691446A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61101047A (en) * 1984-10-23 1986-05-19 エツセジーエツセ　ミクロエレツトロニカ　ソチエタ　ペル　アノニマ Planox method with reduced formation of beak part for forming integrated electronic component element

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5376758A (en) * 1976-12-20 1978-07-07 Nippon Telegr & Teleph Corp <Ntt> Plasma etching method
JPS5455174A (en) * 1977-10-06 1979-05-02 Ibm Etching method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5376758A (en) * 1976-12-20 1978-07-07 Nippon Telegr & Teleph Corp <Ntt> Plasma etching method
JPS5455174A (en) * 1977-10-06 1979-05-02 Ibm Etching method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61101047A (en) * 1984-10-23 1986-05-19 エツセジーエツセ　ミクロエレツトロニカ　ソチエタ　ペル　アノニマ Planox method with reduced formation of beak part for forming integrated electronic component element

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