JPS5683944A - Manufacturing of semiconductor device - Google Patents

Manufacturing of semiconductor device

Info

Publication number
JPS5683944A
JPS5683944A JP16106579A JP16106579A JPS5683944A JP S5683944 A JPS5683944 A JP S5683944A JP 16106579 A JP16106579 A JP 16106579A JP 16106579 A JP16106579 A JP 16106579A JP S5683944 A JPS5683944 A JP S5683944A
Authority
JP
Japan
Prior art keywords
channel
semiconductor device
leading end
layer
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16106579A
Other languages
Japanese (ja)
Inventor
Takashi Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP16106579A priority Critical patent/JPS5683944A/en
Publication of JPS5683944A publication Critical patent/JPS5683944A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L29/78—

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To improve a performance of or yield of a semiconductor device by a method wherein a leading or deepest end of V-channel in the base plate of the semiconductor device is made to have a round form. CONSTITUTION:On N<+> type Si base plate 1 is overlapped P layer 2, P<-> layer 3, channel cut 4, separate insulative layer 5, N dispersion layer 8 and SiO2 film 9. V- channel 10 is formed by KOH solution under a selective opening inner surface of the V-channel is electroyted in HF of about 2.5% for its 50mA/cm<2> or so, resulting in that the leading end is modified to show a curved surface at 10'. Thereafter, when a gate oxide film 11 is formed, a complete intimate continuous film may be formed due to curved surface of the leading end. On the curved leading end surface is selectively formed a poly-Si gate electrode 12. With this arrangement, oxide film having less faults in the leading end of the V-channel may be made, and a concentration of electric field or a poor insulation of the oxide film may be prevented, and thereby a performance and yield of the semiconductor device may be improved.
JP16106579A 1979-12-12 1979-12-12 Manufacturing of semiconductor device Pending JPS5683944A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16106579A JPS5683944A (en) 1979-12-12 1979-12-12 Manufacturing of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16106579A JPS5683944A (en) 1979-12-12 1979-12-12 Manufacturing of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5683944A true JPS5683944A (en) 1981-07-08

Family

ID=15727941

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16106579A Pending JPS5683944A (en) 1979-12-12 1979-12-12 Manufacturing of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5683944A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5023196A (en) * 1990-01-29 1991-06-11 Motorola Inc. Method for forming a MOSFET with substrate source contact
JPH0586954U (en) * 1992-05-06 1993-11-22 ニチバン株式会社 Adhesive tape container with cutter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5023196A (en) * 1990-01-29 1991-06-11 Motorola Inc. Method for forming a MOSFET with substrate source contact
JPH0586954U (en) * 1992-05-06 1993-11-22 ニチバン株式会社 Adhesive tape container with cutter

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