JPS5681955A - Manufacture of semiconductor integrated circuit - Google Patents
Manufacture of semiconductor integrated circuitInfo
- Publication number
- JPS5681955A JPS5681955A JP15949279A JP15949279A JPS5681955A JP S5681955 A JPS5681955 A JP S5681955A JP 15949279 A JP15949279 A JP 15949279A JP 15949279 A JP15949279 A JP 15949279A JP S5681955 A JPS5681955 A JP S5681955A
- Authority
- JP
- Japan
- Prior art keywords
- laminated
- pattern
- wire
- mask
- nh4f
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE:To obtain a wire having high accuracy and reliability by a lift-off by sequentially accumulating metallic layers and metal silicide layers using a mask of inverted taper in cross section. CONSTITUTION:Windows are opened at an SiO2 8 and an Si3N4 9 on a substrate formed with elements, and a PSG11 and a CVD-SiO2 12 are laminated thereon. When a resist mask 13 is coated thereon and the films 11, 12 are etched with NH4F, a pattern 14 of inverted taper is formed due to the difference of etching speeds. The mask 13 is removed, and aluminum 151, 152 and MoSi2 are laminated thereon. When the pattern 14 is etched with NH4F, electrodes 17-19 can be obtained. With this configuration, an ohmic connection to the semiconductor substrate can be improved, and metal silicide excellent for corrosion and heat resistance properties is laminated thereon. Accordingly, even at the time of etching the pattern 14, it can prevent the partial decay and deterioration in the quality of the wire for electrodes and production of hillock due to heat treatment, and there can be obtained a wire having high accuracy and reliability.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15949279A JPS5681955A (en) | 1979-12-08 | 1979-12-08 | Manufacture of semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15949279A JPS5681955A (en) | 1979-12-08 | 1979-12-08 | Manufacture of semiconductor integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5681955A true JPS5681955A (en) | 1981-07-04 |
JPS611892B2 JPS611892B2 (en) | 1986-01-21 |
Family
ID=15694940
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15949279A Granted JPS5681955A (en) | 1979-12-08 | 1979-12-08 | Manufacture of semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5681955A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4902635A (en) * | 1987-12-18 | 1990-02-20 | The Agency Of Industrial Science And Technology | Method for production of compound semicondutor devices |
JPH04129226A (en) * | 1990-09-20 | 1992-04-30 | Nec Yamagata Ltd | Manufacture of semiconductor device |
-
1979
- 1979-12-08 JP JP15949279A patent/JPS5681955A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4902635A (en) * | 1987-12-18 | 1990-02-20 | The Agency Of Industrial Science And Technology | Method for production of compound semicondutor devices |
JPH04129226A (en) * | 1990-09-20 | 1992-04-30 | Nec Yamagata Ltd | Manufacture of semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPS611892B2 (en) | 1986-01-21 |
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