JPS5679353A - Memory bus data transfer method of multiprocessor - Google Patents

Memory bus data transfer method of multiprocessor

Info

Publication number
JPS5679353A
JPS5679353A JP15427079A JP15427079A JPS5679353A JP S5679353 A JPS5679353 A JP S5679353A JP 15427079 A JP15427079 A JP 15427079A JP 15427079 A JP15427079 A JP 15427079A JP S5679353 A JPS5679353 A JP S5679353A
Authority
JP
Japan
Prior art keywords
memory
information
bus
data
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15427079A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6153753B2 (US20110009641A1-20110113-C00256.png
Inventor
Yasushi Fukunaga
Tadaaki Bando
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15427079A priority Critical patent/JPS5679353A/ja
Publication of JPS5679353A publication Critical patent/JPS5679353A/ja
Publication of JPS6153753B2 publication Critical patent/JPS6153753B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Bus Control (AREA)
JP15427079A 1979-11-30 1979-11-30 Memory bus data transfer method of multiprocessor Granted JPS5679353A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15427079A JPS5679353A (en) 1979-11-30 1979-11-30 Memory bus data transfer method of multiprocessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15427079A JPS5679353A (en) 1979-11-30 1979-11-30 Memory bus data transfer method of multiprocessor

Publications (2)

Publication Number Publication Date
JPS5679353A true JPS5679353A (en) 1981-06-29
JPS6153753B2 JPS6153753B2 (US20110009641A1-20110113-C00256.png) 1986-11-19

Family

ID=15580488

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15427079A Granted JPS5679353A (en) 1979-11-30 1979-11-30 Memory bus data transfer method of multiprocessor

Country Status (1)

Country Link
JP (1) JPS5679353A (US20110009641A1-20110113-C00256.png)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58119066A (ja) * 1981-12-30 1983-07-15 ウルリツチ・フインジヤ− デ−タ処理システムにおける１個以上の共通メモリと処理モジユ−ルとの間のデ−タ交換の方法および装置
JPS5977566A (ja) * 1982-09-27 1984-05-04 ニツクスドルフ・コンピユ−タ・アクチエンゲゼルシヤフト 中央クロツク制御多線システムに対する複数のデ−タ処理装置の一つの接続準備方法
JPS60245063A (ja) * 1984-05-21 1985-12-04 Fujitsu Ltd 共用メモリアクセス方式

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58119066A (ja) * 1981-12-30 1983-07-15 ウルリツチ・フインジヤ− デ−タ処理システムにおける１個以上の共通メモリと処理モジユ−ルとの間のデ−タ交換の方法および装置
JPS5977566A (ja) * 1982-09-27 1984-05-04 ニツクスドルフ・コンピユ−タ・アクチエンゲゼルシヤフト 中央クロツク制御多線システムに対する複数のデ−タ処理装置の一つの接続準備方法
JPS6478362A (en) * 1982-09-27 1989-03-23 Nixdorf Computer Ag One connection preparation of several data processors for central clock control multi-line system
JPH0472262B2 (US20110009641A1-20110113-C00256.png) * 1982-09-27 1992-11-17 Jiimensu Nitsukusudorufu Infuomeeshon Shisutemu Ag
JPS60245063A (ja) * 1984-05-21 1985-12-04 Fujitsu Ltd 共用メモリアクセス方式

Also Published As

Publication number Publication date
JPS6153753B2 (US20110009641A1-20110113-C00256.png) 1986-11-19

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