JPS6454578A - Image arithmetic unit - Google Patents

Image arithmetic unit

Info

Publication number
JPS6454578A
JPS6454578A JP21106587A JP21106587A JPS6454578A JP S6454578 A JPS6454578 A JP S6454578A JP 21106587 A JP21106587 A JP 21106587A JP 21106587 A JP21106587 A JP 21106587A JP S6454578 A JPS6454578 A JP S6454578A
Authority
JP
Japan
Prior art keywords
image
data
executed
read out
result
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21106587A
Other languages
Japanese (ja)
Inventor
Tadashi Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jeol Ltd
Original Assignee
Jeol Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jeol Ltd filed Critical Jeol Ltd
Priority to JP21106587A priority Critical patent/JPS6454578A/en
Publication of JPS6454578A publication Critical patent/JPS6454578A/en
Pending legal-status Critical Current

Links

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  • Image Processing (AREA)

Abstract

PURPOSE:To execute the operation at high speed, since every operation can be executed by only reading out a data with a single image converter, by preparing in advance a result of operation to all combinations of plural image data, as a data table. CONSTITUTION:At the time of operation of an image data, the image data is inputted as an address input to an image converter 17 from image memories 13, 14. In this case, for instance, by using high-order 2 bits of an address input data so that the kind of the operation can be known, the result of operation corresponding thereto can be read out of the data table. The read out result of operation is written in an image memory 15, and if necessary, the arithmetic processing is performed again. In this case, since the data table is read out at high speed, the operation of two image data can be executed by one cycle. Accordingly, all the processings can be executed by the timing of a bus clock, and a timing controller can be eliminated.
JP21106587A 1987-08-25 1987-08-25 Image arithmetic unit Pending JPS6454578A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21106587A JPS6454578A (en) 1987-08-25 1987-08-25 Image arithmetic unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21106587A JPS6454578A (en) 1987-08-25 1987-08-25 Image arithmetic unit

Publications (1)

Publication Number Publication Date
JPS6454578A true JPS6454578A (en) 1989-03-02

Family

ID=16599819

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21106587A Pending JPS6454578A (en) 1987-08-25 1987-08-25 Image arithmetic unit

Country Status (1)

Country Link
JP (1) JPS6454578A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03161877A (en) * 1989-11-20 1991-07-11 Ezel Inc Conversion circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03161877A (en) * 1989-11-20 1991-07-11 Ezel Inc Conversion circuit

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