JPS57137944A - General register advance control system - Google Patents

General register advance control system

Info

Publication number
JPS57137944A
JPS57137944A JP2379681A JP2379681A JPS57137944A JP S57137944 A JPS57137944 A JP S57137944A JP 2379681 A JP2379681 A JP 2379681A JP 2379681 A JP2379681 A JP 2379681A JP S57137944 A JPS57137944 A JP S57137944A
Authority
JP
Japan
Prior art keywords
circuit
general register
instruction
inputted
instruction decoding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2379681A
Other languages
Japanese (ja)
Other versions
JPS6126693B2 (en
Inventor
Fumio Hoshi
Teruyoshi Mita
Masao Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2379681A priority Critical patent/JPS57137944A/en
Publication of JPS57137944A publication Critical patent/JPS57137944A/en
Publication of JPS6126693B2 publication Critical patent/JPS6126693B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

PURPOSE:To get rid of a dead loss in executing the operation, and to elevate the processing capacity, by additionally providing an instruction decoding circuit on a storage device, and reading and operating in advance the contents of a general register by an output of this circuit prior to execution of the instruction. CONSTITUTION:To an instruction decoding circuit 10, an output of a storage device 1 is inputted, its output is divided into 2 branches, and one branch is inputted to a general address generating circuit 5 and the other branch is inputted to an operation controlling circuit 6. In the instruction decoding circuit 10, as soon as execution of an instruction is started, A of a general register 4 is read out in the first cycle, and the operation controlling circuit 6 drives the general address generating circuit 5 by an instruction decoding circuit 3 in the second cycle. Since read-out of A of the general register 4 has been completed already, read-out of B of the general register 4 and write of its B are executed continuously, and the operation of A+B is executed by the continuous timing in the machine cycle of 3 cycles.
JP2379681A 1981-02-20 1981-02-20 General register advance control system Granted JPS57137944A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2379681A JPS57137944A (en) 1981-02-20 1981-02-20 General register advance control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2379681A JPS57137944A (en) 1981-02-20 1981-02-20 General register advance control system

Publications (2)

Publication Number Publication Date
JPS57137944A true JPS57137944A (en) 1982-08-25
JPS6126693B2 JPS6126693B2 (en) 1986-06-21

Family

ID=12120280

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2379681A Granted JPS57137944A (en) 1981-02-20 1981-02-20 General register advance control system

Country Status (1)

Country Link
JP (1) JPS57137944A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0239081A2 (en) * 1986-03-26 1987-09-30 Hitachi, Ltd. Pipelined data processor capable of decoding and executing plural instructions in parallel

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0373237A (en) * 1989-08-10 1991-03-28 Okabe Kenzaiten:Kk Method for shunt carrying article in production line and article shunting carrier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0239081A2 (en) * 1986-03-26 1987-09-30 Hitachi, Ltd. Pipelined data processor capable of decoding and executing plural instructions in parallel

Also Published As

Publication number Publication date
JPS6126693B2 (en) 1986-06-21

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