JPS5678242A - Automatic equalizer - Google Patents

Automatic equalizer

Info

Publication number
JPS5678242A
JPS5678242A JP15483579A JP15483579A JPS5678242A JP S5678242 A JPS5678242 A JP S5678242A JP 15483579 A JP15483579 A JP 15483579A JP 15483579 A JP15483579 A JP 15483579A JP S5678242 A JPS5678242 A JP S5678242A
Authority
JP
Japan
Prior art keywords
circuit
circuits
output
gain
peak
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15483579A
Other languages
Japanese (ja)
Inventor
Masaru Yamaguchi
Toru Koyama
Fumio Akashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15483579A priority Critical patent/JPS5678242A/en
Publication of JPS5678242A publication Critical patent/JPS5678242A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03114—Arrangements for removing intersymbol interference operating in the time domain non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals
    • H04L25/03133—Arrangements for removing intersymbol interference operating in the time domain non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals with a non-recursive structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Filters That Use Time-Delay Elements (AREA)

Abstract

PURPOSE:To reduce interference among codes by controlling the gain of a corresponding emphasizing circuit by the control output of a time-axis equalizer equivalent to an observation frequency on a frequency axis and outputs of peak detecting circuits. CONSTITUTION:A flat gain for a received signal is varied by variable gain circuit 2, whose output peak level is detected by peak voltage detecting circuit 10 and the flat gain is controlled by control circuit 11 with the output of this circuit 10 to converge the peak level. A timing signal included in the received signal is extracted by tuning circuit 13 and a clock signal is outputted from slicer 15. Further, emphasizing circuits 91-9N that control the gain of an observation frequency by receiving the output of circuit 2 are provided. Then, the clock signal is multiplied by the output of circuit 2 at multipliers 61-6N and peak levels of the multiplication results are detected by peak level detecting circuits 71-7N; and circuits 91-9N are controlled by control circuits 81-8N receiving outputs of those circuits 71-7N and a signal equalized by time-axis equalizer 17 receiving the clock signal is outputted.
JP15483579A 1979-11-29 1979-11-29 Automatic equalizer Pending JPS5678242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15483579A JPS5678242A (en) 1979-11-29 1979-11-29 Automatic equalizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15483579A JPS5678242A (en) 1979-11-29 1979-11-29 Automatic equalizer

Publications (1)

Publication Number Publication Date
JPS5678242A true JPS5678242A (en) 1981-06-27

Family

ID=15592916

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15483579A Pending JPS5678242A (en) 1979-11-29 1979-11-29 Automatic equalizer

Country Status (1)

Country Link
JP (1) JPS5678242A (en)

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