JPS54102855A - Timing phase control circuit - Google Patents

Timing phase control circuit

Info

Publication number
JPS54102855A
JPS54102855A JP881778A JP881778A JPS54102855A JP S54102855 A JPS54102855 A JP S54102855A JP 881778 A JP881778 A JP 881778A JP 881778 A JP881778 A JP 881778A JP S54102855 A JPS54102855 A JP S54102855A
Authority
JP
Japan
Prior art keywords
timing
phase
control circuit
circuit
discrimination
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP881778A
Other languages
Japanese (ja)
Inventor
Toshihiko Wakahara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP881778A priority Critical patent/JPS54102855A/en
Publication of JPS54102855A publication Critical patent/JPS54102855A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To make it possible to remove deterioration in transmission quality basing upon timing phase deviation, by adding a function of controlling the phase of a timing clock at a discrimination time in the optimum phase invariably. CONSTITUTION:Timing phase information detection circuit 11 and voltage-control variable phase shifter 12 are both provided and discrimination information is extracted from threshold level control circuit 5. In addition, the regenerative repeater including the timing phase control circuit includes impedance converters 2 and 9, line equalizer 3, level converters 4 and 8, discrimination circuit 6, and timing extraction circuit 7. In the constitution like this, the timing regenerative function makes extraction 7 of a timing wave component and then detection 11 of the direction of the timing phase to be controlled; and the information is converted into a voltage, which controlled 12 to the optimum position before being discriminated 6.
JP881778A 1978-01-31 1978-01-31 Timing phase control circuit Pending JPS54102855A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP881778A JPS54102855A (en) 1978-01-31 1978-01-31 Timing phase control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP881778A JPS54102855A (en) 1978-01-31 1978-01-31 Timing phase control circuit

Publications (1)

Publication Number Publication Date
JPS54102855A true JPS54102855A (en) 1979-08-13

Family

ID=11703356

Family Applications (1)

Application Number Title Priority Date Filing Date
JP881778A Pending JPS54102855A (en) 1978-01-31 1978-01-31 Timing phase control circuit

Country Status (1)

Country Link
JP (1) JPS54102855A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5657354A (en) * 1979-10-17 1981-05-19 Fujitsu Ltd Phase control circuit
JPS56136065A (en) * 1980-03-27 1981-10-23 Victor Co Of Japan Ltd Data regenerator
WO1988005235A1 (en) * 1987-01-12 1988-07-14 Fujitsu Limited Discrimination timing control circuit
EP0389874A2 (en) * 1989-03-16 1990-10-03 Fujitsu Limited Phase shift circuit and repeater using the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49129463A (en) * 1973-04-10 1974-12-11
JPS49129468A (en) * 1973-04-10 1974-12-11

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49129463A (en) * 1973-04-10 1974-12-11
JPS49129468A (en) * 1973-04-10 1974-12-11

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5657354A (en) * 1979-10-17 1981-05-19 Fujitsu Ltd Phase control circuit
JPS56136065A (en) * 1980-03-27 1981-10-23 Victor Co Of Japan Ltd Data regenerator
JPH0334266B2 (en) * 1980-03-27 1991-05-22 Victor Company Of Japan
WO1988005235A1 (en) * 1987-01-12 1988-07-14 Fujitsu Limited Discrimination timing control circuit
US4912726A (en) * 1987-01-12 1990-03-27 Fujitsu Limited Decision timing control circuit
EP0389874A2 (en) * 1989-03-16 1990-10-03 Fujitsu Limited Phase shift circuit and repeater using the same
US5088106A (en) * 1989-03-16 1992-02-11 Fujitsu Limited Phase shift circuit and repeater using the same

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