JPS5724113A - Digital filter device - Google Patents

Digital filter device

Info

Publication number
JPS5724113A
JPS5724113A JP9951480A JP9951480A JPS5724113A JP S5724113 A JPS5724113 A JP S5724113A JP 9951480 A JP9951480 A JP 9951480A JP 9951480 A JP9951480 A JP 9951480A JP S5724113 A JPS5724113 A JP S5724113A
Authority
JP
Japan
Prior art keywords
output
adder
delay circuit
circuit
multiplier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9951480A
Other languages
Japanese (ja)
Other versions
JPS6337974B2 (en
Inventor
Shigenori Sano
Kotaro Hanzawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP9951480A priority Critical patent/JPS5724113A/en
Publication of JPS5724113A publication Critical patent/JPS5724113A/en
Publication of JPS6337974B2 publication Critical patent/JPS6337974B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/04—Recursive filters
    • H03H17/0461—Quantisation; Rounding; Truncation; Overflow oscillations or limit cycles eliminating measures

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Control Of Amplification And Gain Control (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To keep the maximum value of amplitude characteristics and to prevent the distortion of waveform, by detecting the overflow of processing data and making overflow processing and gain control. CONSTITUTION:An input data is supplied to an overflow processing circuit 4 via a multiplier 1 and an adder 3, and after it is in overflow processing, it is applied to a delay circuit 5 and an adder 6. The output of the delay circuit 5 is doubled at a multiplier 7 and applied to the adder 6, the output of the adder 6 and the output of a delay circuit 11 delaying the output of the delay circuit 5 further are added at an adder 8 to obtain the output of a digital filter device. A gain control circuit 13 applies an output to the adder 2 based on the output of the overflow processing circuit 4 and the gain of the filter is controlled by controlling the coefficient of the multiplier 1.
JP9951480A 1980-07-21 1980-07-21 Digital filter device Granted JPS5724113A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9951480A JPS5724113A (en) 1980-07-21 1980-07-21 Digital filter device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9951480A JPS5724113A (en) 1980-07-21 1980-07-21 Digital filter device

Publications (2)

Publication Number Publication Date
JPS5724113A true JPS5724113A (en) 1982-02-08
JPS6337974B2 JPS6337974B2 (en) 1988-07-27

Family

ID=14249353

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9951480A Granted JPS5724113A (en) 1980-07-21 1980-07-21 Digital filter device

Country Status (1)

Country Link
JP (1) JPS5724113A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63263909A (en) * 1987-04-22 1988-10-31 Victor Co Of Japan Ltd Peak display device for preventing overload in digital signal arithmetic unit
JPS63292716A (en) * 1987-05-25 1988-11-30 Victor Co Of Japan Ltd Peak display device for preventing overload in arithmetic unit for digital signal

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63263909A (en) * 1987-04-22 1988-10-31 Victor Co Of Japan Ltd Peak display device for preventing overload in digital signal arithmetic unit
JPS63292716A (en) * 1987-05-25 1988-11-30 Victor Co Of Japan Ltd Peak display device for preventing overload in arithmetic unit for digital signal

Also Published As

Publication number Publication date
JPS6337974B2 (en) 1988-07-27

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