JPS5671948A - Ic chip - Google Patents
Ic chipInfo
- Publication number
- JPS5671948A JPS5671948A JP14889579A JP14889579A JPS5671948A JP S5671948 A JPS5671948 A JP S5671948A JP 14889579 A JP14889579 A JP 14889579A JP 14889579 A JP14889579 A JP 14889579A JP S5671948 A JPS5671948 A JP S5671948A
- Authority
- JP
- Japan
- Prior art keywords
- check
- electrodes
- electrode
- dummy
- bump electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
PURPOSE:To ensure accurate size measuring by keeping upon the check of electric characteristic one or two dummy bump electrodes provided in addition to bump electrodes for the check faultless when the electrodes are shaped semispherical or into a table form on an IC chip using solder. CONSTITUTION:A plurality of semispherical or table-shaped solder bump electrodes 2 are provided on the both sides of an IC chip body 1 to check electric characteristic. Besides, one dummy solder bump electrode 3 or two dummy solder bump electrodes 4 are provided which are not used for check. The electrode 2 is used to check electrode characteristic but the electrodes 3 or 4 are left not used for check. Thereby, even if the electrode is deformed upon the contact of a probe, the electrodes 3 or 4 are kept faultless so that size measuring can be made accurately.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14889579A JPS5671948A (en) | 1979-11-19 | 1979-11-19 | Ic chip |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14889579A JPS5671948A (en) | 1979-11-19 | 1979-11-19 | Ic chip |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5671948A true JPS5671948A (en) | 1981-06-15 |
Family
ID=15463083
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14889579A Pending JPS5671948A (en) | 1979-11-19 | 1979-11-19 | Ic chip |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5671948A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS617640A (en) * | 1984-06-22 | 1986-01-14 | Toshiba Corp | Method and apparatus for testing characteristic of integrated circuit device |
-
1979
- 1979-11-19 JP JP14889579A patent/JPS5671948A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS617640A (en) * | 1984-06-22 | 1986-01-14 | Toshiba Corp | Method and apparatus for testing characteristic of integrated circuit device |
JPH0347581B2 (en) * | 1984-06-22 | 1991-07-19 | Tokyo Shibaura Electric Co |
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