JPS617640A - Method and apparatus for testing characteristic of integrated circuit device - Google Patents

Abstract

PURPOSE:To accurately detect an abnormality generating position in the interior of an integrated circuit device even in a state that the sealing cap body is being adhered on the device by a method wherein conductor patterns not being directly connected electrically with the terminal pins of the substrate and exposed conductor pads connected electrically with the conductor patterns are formed. CONSTITUTION:Conductor patterns 2 are formed on the surface layer part 1a and the internal layer part 1b of a ceramic multilayer substrate 1. Exposed conductor pads 7 are formed on the side of the face of one side of this substrate 1, whereon IC chips 4 are not mounted, in such a way as to array in a lattice type. These pads 7 are electrically connected with the conductor patterns 2, which are not directly connected electrically with the terminal pins 3 of the substrate 1. According to this constitution, when abnormality is perceived in the interior of the IC device, a measurement of the voltage value, the resistance and so forth in each position of the patterns 2 in the interior is performed through the pads 7 before a sealing cap body 6 is dismantled, thereby enabling to accurately grasp the abnormality generating position.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention particularly relates to a method and apparatus for testing the characteristics of a multi-chip package type integrated circuit device.

[Technical Background of the Invention] In recent years, various types of multi-chip package integrated circuit devices in which multiple IC chips are mounted in one package have been developed in response to the increasing density of electronic equipment parts. .

For example, as shown in FIG. 3, such a multi-chip package type integrated circuit device has a conductor pattern 2 formed on the surface layer portion 1aF3 and the inner layer portion 1b, and terminal pins 3, 3, . A plurality of IC chips 4.4, ... and passive components 5.5, ... such as capacitors are mounted on the exposed ceramic multilayer substrate 1, and these are electrically connected to the conductor pattern 2. A structure in which the sealing lid 6 is roughly fixed is known.

By the way, when manufacturing such a multi-chip package type integrated circuit device, an electrical characteristic test is performed after each component is processed and assembled.

Generally, this electrical characteristic test is performed by bringing a probe of a characteristic testing device into contact with each part of the conductor pattern 2 and measuring the voltage value, resistance value, etc. before fixing the sealing lid 6. However, IC chip 4.4 due to external light...
In consideration of the change in the characteristics, the characteristic test is also conducted after the sealing lid 6 is fixed.

In this case, each measurement is performed by bringing the measurement terminals of the characteristic testing device into contact with the terminal pins 3, 3, . . . extending from the ceramic multilayer substrate 1.

[Problems with the background art] However, since the characteristics of integrated circuit devices have many parameters, it is not possible to perform a complete characteristic test by measuring only from the terminal pins 3, 3, etc., and abnormalities may occur. Even if it is recognized, it is difficult to accurately determine the location where it occurs. Therefore, in order to accurately determine the location of the abnormality, it is necessary to remove the sealing lid 6 and measure the internal connections, but it is necessary to measure the characteristics of the IC chip in its sealed state and in its exposed state. If the values are different, there is a possibility that the abnormality itself will not be detected if the sealing lid is removed.

Furthermore, when an integrated circuit device is constructed using a VLSI IC chip, the conductor pattern 2 is densely formed and the internal connections are complicated, making measurement extremely difficult. there were.

[Object of the Invention] The present invention has been made in view of the above-mentioned conventional circumstances.
A method for testing the characteristics of an integrated circuit device that can accurately detect the location of an internal abnormality even when a sealing lid is attached, and a characteristics testing device that can perform the characteristics test extremely easily. This is what we are trying to provide.

[Summary of the Invention] That is, the present invention forms exposed conductor pads electrically connected to conductor patterns that are not directly electrically connected to terminal pins on the side of the substrate of an integrated circuit device on which no IC chip is mounted. , a method for testing the characteristics of an integrated circuit device, characterized in that the characteristics are tested through the exposed conductor pad;
In a characteristic testing apparatus configured to perform a characteristic test by mounting an integrated circuit device on a test object mounting section, a socket is provided at a position corresponding to a terminal pin of the integrated circuit device on the test object mounting section. The characteristics testing device is characterized in that a plurality of elastic contact terminals are provided at predetermined positions between the sockets.

[Embodiment of the Invention] The details of the present invention will be described below with reference to an embodiment shown in the drawings.

FIG. 1 is a cross-sectional view showing an integrated circuit device to which the method of the present invention is applied, and parts common to those in FIG. 3 described above are given the same reference numerals.

In the figure, reference numeral 1 indicates a ceramic multilayer substrate, and a conductor pattern 2 is formed on a surface layer portion 1a and an inner layer portion 1b. Furthermore, terminal pins 3, 3, . . . for mounting extend from the edge of the ceramic multilayer substrate 1. In addition,
These terminal pins 3.3, . . . are directly electrically connected to a portion of the conductor pattern 2. A relatively large number of IC chips 4.4 are mounted on the ceramic multilayer substrate 1.
・Passive components such as decoupling capacitors 5.5
, . . . are mounted, and these are electrically connected to predetermined portions of the conductive pattern 2. Furthermore, a sealing lid body 6 made of Kovar or the like is fixed to cover these by, for example, soldering or brazing.

The above parts have the same structure as a conventionally used multi-chip integrated circuit device, but in the integrated circuit device to which the method of the present invention is applied, the surface layer 1c of the ceramic multilayer substrate 1, that is, the IC chip 4 .4, . . are not mounted, exposed conductor pads 7, 7, . . . are formed so as to be arranged in a grid pattern.

These exposed conductor pads 7.7, . . . are portions of the conductor pattern 2 that are not directly electrically connected to the terminal pins 3.3, .
It is electrically connected to the connection portion between the C chip and passive components.

The method of the present invention measures the voltage value, resistance value, etc. at each position of the internal conductor pattern 2 through the exposed conductor pads 7, 7, . . . of the integrated circuit device constructed as described above.

Therefore, according to the method of the present invention, if an abnormality is found inside the integrated circuit device and it is necessary to remove the sealing lid 6 and replace the IC chip 4 or the passive components 5, or change the bonding, etc. However, since the location of the abnormality can be accurately determined by measuring before removing the sealing lid 6,
Plans for replacement or change work can be immediately determined.

Furthermore, even when performing a characteristic test before fixing or removing the sealing lid 6, the exposed conductor pads 7, 7, . . .
・By connecting to the characteristic test equipment through the probe, positioning of the probe contact position, etc. becomes easy, and the number of steps involved in measurement is greatly reduced.

FIG. 2 is a diagram illustrating the configuration of the characteristic testing apparatus of the present invention.

The figure shows the integrated circuit device A shown in FIG.
FIG. 2 is a cross-sectional view showing a state in which the characteristic testing apparatus B of the present invention is mounted on a test object mounting section.

A socket 9.9 is provided in the test object mounting portion of this characteristic testing apparatus B at a position corresponding to the terminal pins 3.3, . . . to the integrated circuit device on the board 8. .9
At the position corresponding to the exposed conductor pads 7.7, . . .
Elastic contact terminals 10, 10, . . . , which will be described later, are provided in a protruding manner.

and a socket 9.9 and an elastic contact terminal 10.10
1 . . . are electrically connected to the input/output section of the equipment to be measured by a conductor pattern (not shown) on the substrate 8 or wire wrapping.

The elastic contact terminals 10.10, . . . are generally spring-loaded.
This is a terminal component called a contact probe or pogo pin, and includes a cylindrical body 10a made of a conductor and a cylindrical body 10a made of a conductor.
The conductor rod 10b is housed in a conductor rod 10a and is urged outward by a coil spring (not shown).

The conductor rod 10b connects the terminal pins 3.3, .
. . is inserted into the socket 9.9, the top portion 10C contacts the exposed conductor pads 7.7, . . . with a certain degree of pressing force. As a result, conductor pattern 2 of integrated circuit device A
, including the portions not directly connected to the terminal pins 3.3, . . . , are reliably connected to the measuring equipment.

and terminal pins 3.3, for example to the integrated circuit device.
- Standard input/output characteristics and exposed conductor pads from 7.
7. By inputting standard voltage values, resistance values, etc. between Characteristic tests can be performed simply by attaching it to the body attachment part.

Although the above embodiment describes the case where the present invention is applied to a DIP type integrated circuit device, the present invention should not be limited to such a single embodiment (such as a DIP type, flat package type, etc.). The same configuration can be applied to integrated circuit devices in various packages such as the above.

[Effects of the Invention] As explained above, according to the method for testing the characteristics of an integrated circuit device of the present invention, in particular, the surface layer of the substrate of a multi-chip integrated circuit device has a conductive pattern directly connected to a terminal pin. Provide an exposed conductor pad connected to the non-conducting part,
Since the characteristic test is conducted through the exposed conductor pads, it is possible to accurately determine the location of internal abnormality even with the sealing lid still attached.

Furthermore, the characteristic testing device of the present invention has sockets arranged at positions corresponding to the terminal pins of the integrated circuit device, and elastic contact terminals protruding from predetermined positions between the sockets, so that characteristic tests can be carried out extremely easily. Can be done.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the structure of an integrated circuit device to which the present invention is applied, FIG. 2 is a cross-sectional view showing the structure of the main part of the characteristic testing device of the present invention, and FIG. FIG. 2 is a cross-sectional view showing the structure of the integrated circuit device in the package. 1... Ceramic multilayer substrate 2...
・・・・・・・・・Conductor pattern 3・・・・・・・・・
・・・Terminal pin 4・・・・・・・・・IC chip 5・・・・・・
...Passive component 6 ... Sealing lid 7 ...... Exposed conductor pad 8 ...
・・・・・・・・・Plate 9・・・・・・・・・・・・Socket 10・・・・・・・・・・Elastic contact terminal Patent attorney Satoshi Suyama - 1st Figure 3

Claims (2)

[Claims] (1) Forming exposed conductor pads electrically connected to conductor patterns that are not directly electrically connected to terminal pins on the side of the substrate of the integrated circuit device on which the IC chip is not mounted,
A method for testing the characteristics of an integrated circuit device, characterized in that the characteristics are tested through the exposed conductor pads. (2) In a characteristic testing apparatus configured to perform a characteristic test by mounting an integrated circuit device on a test object mounting section, a socket is installed at a position corresponding to a terminal pin of the integrated circuit device on the test object mounting section. A characteristic testing device characterized in that a plurality of elastic contact terminals are provided at predetermined positions between the sockets.