US20230207401A1 - Analog sense points for measuring circuit die - Google Patents

Analog sense points for measuring circuit die Download PDF

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Publication number
US20230207401A1
US20230207401A1 US17/561,396 US202117561396A US2023207401A1 US 20230207401 A1 US20230207401 A1 US 20230207401A1 US 202117561396 A US202117561396 A US 202117561396A US 2023207401 A1 US2023207401 A1 US 2023207401A1
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circuit
analog sense
circuit die
substrate
sense points
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US17/561,396
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Christopher F. Kinney
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Micron Technology Inc
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Micron Technology Inc
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Priority to US17/561,396 priority Critical patent/US20230207401A1/en
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KINNEY, CHRISTOPHER F
Priority to CN202211540017.7A priority patent/CN116338419A/en
Publication of US20230207401A1 publication Critical patent/US20230207401A1/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2884Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/2805Bare printed circuit boards
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/2818Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP] using test structures on, or modifications of, the card under test, made for the purpose of testing, e.g. additional components or connectors
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2886Features relating to contacting the IC under test, e.g. probe heads; chucks
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2896Testing of IC packages; Test features related to IC packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52Mounting semiconductor bodies in containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector

Definitions

  • Embodiments of the disclosure relate generally to voltage measurement and, more specifically, to analog sense points for a circuit die, which can form part of an integrated circuit (IC) package and facilitate measurement of at least a portion of the circuit die using a Kelvin method of measurement.
  • IC integrated circuit
  • the manufactured circuit can include one or more interfaces that enable measurement of signals or voltages generated by the manufactured circuit using external measuring instruments. For instance, while the manufactured circuit is operating, one or more probes of a measuring instruments can be coupled to an interface of a circuit, which can facilitate measurement of a signal or voltage passing through a portion of the circuit. Additionally, a standard interface, such as a JTAG (Joint Test Action Group) interface, can be used in some instances to provide certain measurements as digital data.
  • JTAG Joint Test Action Group
  • FIG. 1 illustrates an example of analog sense points for a circuit die, in accordance with some embodiments of the present disclosure.
  • FIG. 2 illustrates example analog sense points implemented with respect to a substrate of an integrated circuit package, in accordance with some embodiments of the present disclosure.
  • FIG. 3 is a flowchart illustrating an example method for using analog sense points to measure a circuit die, in accordance with some embodiments of the present disclosure.
  • FIG. 4 is a flowchart illustrating an example method for manufacturing a circuit that includes analog sense points to measure a circuit die, in accordance with some embodiments of the present disclosure.
  • aspects of the present disclosure are directed to analog sense points for circuit die (or die), which can form part of an integrated circuit (IC) package (e.g., memory circuit die on an IC package) and can facilitate measurement (e.g., voltage measurement) of a portion of the circuit die using a Kelvin method of measuring.
  • IC integrated circuit
  • some embodiments provide for one or more analog sense points disposed on a circuit substrate or substrate, such as a printed circuit board (PCB), of an integrated circuit (IC) package, where the one or more analog sense points facilitate a measurement with respect to a die of the IC package that is mounted on the substrate.
  • PCB printed circuit board
  • an embodiment described herein can be implemented with respect to a circuit die of a memory sub-system.
  • a memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and memory module.
  • a host system can utilize a memory sub-system that includes one or more memory components (also hereinafter referred to as “memory devices”). The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.
  • IC packages often rely on digital methods for measuring voltage of the IC packages. Such digital methods usually provide the voltage measurement as digital data via a JTAG (Joint Test Action Group) or similar interface on the IC package.
  • JTAG Joint Test Action Group
  • IC packages suffer from high resistance and inductance, which can result in errors in the measuring provided by the digital methods. Additionally, resolution provided by digital voltage measurement methods can be limited.
  • Kelvin sense points facilitate a Kelvin method for measuring a circuit (e.g., voltage, current, resistance, or impedance thereof) with reduced measurement errors.
  • a Kelvin method of measurement (also referred to as four-point sensing) is an analog method of measurement, which can be used to measure voltage via four sense points (e.g., probes or electrodes)—one pair of points (also referred to as force points) that is used to measure resistance or impedance (hereafter, resistance/impedance) of a portion of a circuit (e.g., by driving a known current through a portion of a circuit) and another pair of points (also referred to as sense points) that is used to measure voltage of the portion.
  • sense points e.g., probes or electrodes
  • the other pair of points can be used to measure voltage of the portion based on a known or unknown current already flowing through the portion during operation of the circuit.
  • two sense points e.g., Kelvin sense points
  • four points e.g., Kelvin sense points
  • Use of a Kelvin method can avoid measurement errors (e.g., voltage measurement errors) that result from inductance or resistance in wires of a circuit.
  • Kelvin voltage sense points are useful in measuring a voltage of a circuit, Kelvin voltage sense points are not currently used with respect to IC packages.
  • one or more analog sense points are disposed, or embedded, on a top layer (e.g., top side) of a substrate of an IC package, which can facilitate accurate voltage measurement of at least a portion of a circuit die (or die) of the IC package that is mounted on the substrate.
  • the one or more analog sense points disposed on the top layer of the substrate can facilitate a Kelvin method for measuring a voltage of the die.
  • the one or more analog sense points can serve as Kelvin sense points and facilitate a Kelvin connection between the die and one or more measuring instruments, such as an oscilloscope, a voltmeter, a galvanometer, or a multimeter.
  • the one or more analog sense points comprises one pair of analog sense points that is used to measure voltage of the portion. These two (Kelvin) sense points for measuring voltage has little or no current flowing along its sense lines and, thus, the resistance and inductance do not affect the voltage measurement.
  • the one or more analog sense points comprises one pair of analog sense points that is used to measure resistance/impedance of the portion, and another pair of analog sense points that is used to measure voltage of the portion.
  • the first pair of analog sense points can be conductively coupled to outer probe points with respect to the portion, while the second pair of analog sense points can be conductively coupled to inner probe points that are closer with respect to the portion.
  • the substrate can comprise a printed circuit board (PCB) of an IC package.
  • PCB printed circuit board
  • high frequency voltages generated by the die can be measured, such as voltages at 1-10 GHz.
  • the one or more analog sense points comprise one or more conductive pads (e.g., metal pads) disposed on the substrate.
  • an analog sense pad can comprise a solder bump (or bump) disposed on a conductive pad.
  • the die of the IC package can comprise a flip-chip BGA or a wire bond chip with a BGA mounted on the substrate.
  • An analog sense pad can be operatively coupled to the die of the IC package by way of a conductive path (e.g., a wire or a trace) disposed on the substrate.
  • one or more analog sense points are disposed at or near a periphery or edge of an IC package.
  • the one or more analog sense points can be disposed where there is less route density than, for example, near a die at a center of the IC package, thereby enabling the one or more analog sense points to have larger dimensions than would otherwise be possible.
  • Some embodiments can be implemented by removing one or more of a package lid, encapsulant, and solder mask of an IC package to expose one or more conductive pads (e.g., metal pads) to be used as one or more analog sense pads.
  • a voltage measurement using top-layer, analog sense points of an embodiment can enable testing and debugging of an IC package, while at least reducing voltage measurement errors.
  • the top of a substrate outside the circuit die area can be exposed and used for probe points (e.g., with the lid removal description).
  • various embodiments can provide measurement of voltage at a circuit die, including high-frequency voltage (e.g., 1-10 GHz), with a higher level of resolution and accuracy than traditional methodologies. Additionally, the analog sense pads described herein can provide measurement of a voltage at a circuit die while reducing or avoiding measurement errors caused by resistance of the IC package or filtering (e.g., of high-frequency voltage) caused by inductance of the IC package. Top layer voltage sense pads of an embodiment can obviate the need for extra bottom side pins for an IC package, which can be expensive and can increase the footprint of the IC package.
  • some embodiments can be used as an alternative to using a digital method for measuring voltage of a circuit of an IC package, which can provide a less accurate voltage measurement.
  • the use of some embodiments provides physical access for measuring voltage of a portion of a circuit die (e.g., by placing exposed points on the top of a substrate, regardless of if a lid is used or not), where physical access to a circuit die for such a measurement would be otherwise difficult.
  • Conventional substrate connections at a circuit die are generally not accessible, and lie on top of the substrate and connects between. For conventional substrate connections, there is also no room at the bottom of the package pins since these are reserved (e.g., for important signals and power).
  • analog sense points can be implemented by different means. Additionally, though various embodiments are described herein with respect to measuring voltage, it will be understood that for some embodiments the analog sense points can be used to measure other aspects of a circuit die, such as resistance/impedance or current.
  • a Kelvin method for measuring can also be referred to as four-wire sensing or four-point probes method.
  • a measuring instrument can comprise a device that measures voltage, current, resistance, impedance, or some combination thereof with respect to a circuit. Examples of measuring instruments can include oscilloscopes, voltmeters, galvanometers, and multimeters.
  • IC packages that include or use voltage sense points as described herein, which can be used to measure voltage using a Kelvin method.
  • FIG. 1 illustrates an example of analog sense points 102 , 104 , 110 , 112 for a circuit die 130 , in accordance with some embodiments of the present disclosure.
  • FIG. 1 only presents a simplified representation of analog sense points, on a substrate, that are operatively coupled to a circuit die mounted to the substrate, and excludes additional details that would be typically found in a real-world application of an embodiment.
  • a circuit 100 comprises a substrate 120 , a circuit die 130 mounted on a top side of the substrate 120 , and analog sense points 102 , 104 , 110 , 112 disposed on the top side of the substrate 120 .
  • the analog sense points 102 , 104 , 110 , 112 are disposed at or near the outer perimeter or edge of the substrate 120 , which enables the analog sense points 102 , 104 , 110 , 112 to avoid route congestion at or near the circuit die 130 that would limit the size of the analog sense points 102 , 104 , 110 , 112 .
  • each of the analog sense points 102 , 104 , 110 , 112 can comprise a conductive pad (e.g., metal pad), which can further have a solder ball (e.g., bump) disposed thereon.
  • the substrate 120 comprises a printed circuit board.
  • a plurality of connections can be disposed on a bottom side of the substrate 120 .
  • a pin grid array or a ball grid array can be disposed on the bottom side of the substrate 120 , which can enable the substrate 120 to operatively couple to a larger circuit (e.g., a larger printed circuit board having a chip socket configured to receive and operatively couple to the substrate 120 ).
  • a larger circuit e.g., a larger printed circuit board having a chip socket configured to receive and operatively couple to the substrate 120 .
  • the analog sense points 102 , 104 , 110 , 112 By disposing the analog sense points 102 , 104 , 110 , 112 on the top side of the substrate 120 , various embodiments can obviate the need for extra connection (e.g., conductive) elements (e.g., pins or balls) disposed on the bottom side of the substrate 120 . This can not only reduce the overall cost of manufacturing the circuit 100 ,
  • the analog sense points 102 , 104 , 110 , 112 are conductively coupled to a portion 136 of the circuit die 130 by way of conductive paths 132 .
  • One or more of the conductive paths 132 can comprise a wire or trace disposed on the top side of the substrate 120 .
  • the circuit die 130 can comprise, for example, a flip-chip ball grid array (BGA), where the conductive paths 132 couple the analog sense points 102 , 104 , 110 , 112 to connection elements 134 (e.g., solder ball or bumps) of the ball grid array of the circuit die 130 , and where the connection elements 134 couple to corresponding points with respect to portion 136 .
  • BGA flip-chip ball grid array
  • the circuit die 130 can comprise a wire bond ball grid array (BGA), where wires couple the analog sense points 102 , 104 , 110 , 112 to connection elements of the ball grid array on a top side of the circuit die 130 (e.g., by way another substrate disposed on the ball grid array of the circuit die 130 ).
  • BGA wire bond ball grid array
  • the top side of the substrate 120 and the circuit die 130 can be covered by an epoxy (or other filling) such that the epoxy (or other filling) is not disposed over the analog sense points 102 , 104 , 110 , 112 .
  • the epoxy can be removed from above the analog sense points 102 , 104 , 110 , 112 , thereby providing probe access to the analog sense points 102 , 104 , 110 , 112 .
  • the portion 136 can represent one or more components of the circuit die 130 .
  • the analog sense points 102 , 104 are configured to provide a resistance or impedance measurement for the portion 136
  • the analog sense points 110 , 112 are configured to provide a voltage measurement across the portion 136 .
  • the analog sense points 110 , 112 are coupled closer on the conductive path of the portion 136 than the analog sense points 102 , 104 .
  • one or more measuring instruments e.g., probes thereof
  • the analog sense points 102 , 104 can represent force points or probes
  • the analog sense points 110 , 112 can represent sense points or probes.
  • the one or more measuring instruments can measure a high-frequency voltage (e.g., 1-10 Ghz) at the circuit die 130 (across the portion 136 ), can do so with a higher resolution than traditional technologies, and can do so while avoiding measurement errors (e.g., caused by resistance or inductance caused by IC packaging, etc.).
  • FIG. 2 illustrates example analog sense points implemented with respect to a substrate 200 of an IC package, in accordance with some embodiments of the present disclosure.
  • a top side of the substrate 200 includes analog sense pads 210 , 212 , 214 , 216 , which are conductively coupled to the center portion 220 of the substrate 200 .
  • the center portion 220 of the substrate 200 corresponds to a location on the substrate 200 where a circuit die would mount, and operatively couple, to the substrate 200 .
  • the traces disposed on the substrate 200 can couple to connection elements of a circuit die mounted to the substrate 200 .
  • those traces can couple one or more of the analog sense pads 210 , 212 , 214 , 216 to corresponding connection elements of the circuit die, which can facilitate one or more Kelvin connections with one or more portions of the circuit die as described herein.
  • FIG. 3 is a flowchart illustrating an example method 300 for using analog sense points to measure a circuit die, in accordance with some embodiments of the present disclosure.
  • the method 300 can be performed with respect to the circuit 100 of FIG. 1 or with respect to the substrate 200 of FIG. 2 .
  • the method 300 can be performed during testing or debugging of a circuit, or more specifically, the circuit die coupled to the analog sense points.
  • a user can remove a package lid, encapsulant, a solder mask, or some combination thereof from a circuit (e.g., 100 ), which can expose analog sense points (e.g., 102 , 104 , 110 , 112 ) of the circuit (e.g., 100 ) and render them accessible by probes of one or more measuring instruments. Operation 302 can be performed where the circuit (e.g., 100 ) forms part of a IC package.
  • a user couples one or more measuring instruments to a plurality of analog sense points (e.g., 102 , 104 , 110 , 112 ) of a circuit (e.g., 100 ) comprising the analog sense points and a circuit die (e.g., 130 ).
  • the circuit e.g., 100
  • the circuit comprises a substrate (e.g., 120 ) having a top side
  • the circuit die e.g., 130
  • the circuit die is mounted to the top side of the substrate (e.g., 120 ).
  • analog sense points e.g., 102 , 104 , 110 , 112
  • the analog sense points are disposed on the top side of the substrate (e.g., 120 ), and the analog sense points are operatively coupled to the circuit die (e.g., 130 ) such that the analog sense points are configured to provide a voltage measurement for a portion (e.g., 136 ) of the circuit die (e.g., 130 ).
  • the analog sense points (e.g., 102 , 104 , 110 , 112 ) comprise a first sub-plurality (e.g., pair) of analog sense points (e.g., 110 , 112 ) for measuring voltage of the portion (e.g., 136 ) and a second sub-plurality (e.g., pair) of analog sense points (e.g., 102 , 104 ) for measuring resistance or impedance of the portion (e.g., 136 ).
  • a first sub-plurality e.g., pair
  • analog sense points e.g., 110 , 112
  • a second sub-plurality e.g., pair
  • the one or more measuring instruments can be coupled to the analog sense points (e.g., 102 , 104 , 110 , 112 ) such that voltage probes of the one or more measuring instruments are coupled to the first sub-plurality of analog sense points (e.g., 110 , 112 ), and current/resistance/impedance probes of the one or more measuring instruments are coupled to the second sub-plurality of analog sense points (e.g., 102 , 104 ).
  • analog sense points e.g., 102 , 104 , 110 , 112
  • first sub-plurality of analog sense points e.g., 110 , 112
  • current/resistance/impedance probes of the one or more measuring instruments are coupled to the second sub-plurality of analog sense points (e.g., 102 , 104 ).
  • voltage of the portion is measured by the first sub-plurality of analog sense points (e.g., 110 , 112 ).
  • Resistance can be without any time varying signal (e.g., direct current(DC)), and impedance can be with a time varying signal (e.g., alternating current (AC)), where impedance includes resistance plus the effects of inductance and capacitance.
  • DC direct current
  • AC alternating current
  • a voltage of the portion is measured by the one or more measuring instruments using a Kelvin method of measurement.
  • the one or more measuring instruments used can include, without limitation, an oscilloscope, a voltmeter, a galvanometer, or a multimeter.
  • FIG. 4 is a flowchart illustrating an example method 400 for manufacturing a circuit that includes analog sense points to measure a circuit die, in accordance with some embodiments of the present disclosure.
  • the method 400 can be used to manufacture a circuit similar to the circuit 100 of FIG. 1 or a substrate similar to the substrate 200 of FIG. 2 .
  • a circuit die is manufactured that includes a plurality of external connection elements (e.g., pins, bumps, or solder balls) that are configured to provide a Kelvin connection with a portion (e.g., internal component or electrical path) of the circuit die.
  • a portion e.g., internal component or electrical path
  • the circuit die comprises a ball grid array (BGA) as part of its external connection elements
  • BGA ball grid array
  • connection elements e.g., four connection elements of 134 of FIG. 1
  • the ball grid array e.g., bumps or solder balls
  • the circuit die can include internal routing or wiring that operatively couples the at least four connection elements to the portion of the circuit die such that when one or more measuring instruments are coupled to the at least two connections (by way of analog sense pads on the substrate), a Kelvin connection is formed between the one or more measuring instruments and the portion of the circuit die.
  • the external connection elements e.g., at least four connection elements of the ball grid array
  • the external connection elements can be positioned such that once the circuit die is mounted to a substrate as described herein, those external connection elements operatively couple to conductive paths (e.g., wires or traces) on the substrate that operatively couple to analog sense pads on the substrate.
  • a substrate e.g., 120 of FIG. 1
  • the substrate comprises a plurality of analog sense points (e.g., 102 , 104 , 110 , 112 of FIG. 1 ) disposed on a side of the substrate, and a plurality of conductive paths (e.g., 132 of FIG. 1 ) operatively coupling the plurality of analog sense points to a (mount) location, on the side of the substrate, configured to receive a circuit die (e.g., location on the substrate 120 that receives 134 of FIG. 1 ).
  • the conductive paths can comprise wires or traces disposed on the substrate.
  • the circuit die manufactured at operation 402 is mounted to the mount location on the substrate such that the circuit die is operatively coupled to the plurality of analog sense points (e.g., 102 , 104 , 110 , 112 of FIG. 1 ) by way of the plurality of conductive paths (e.g., 132 of FIG. 1 ).
  • the plurality of analog sense points can provide a voltage measurement for the portion (e.g., 136 of FIG. 1 ) of the circuit die, and can do so by way of a Kelvin connection as described herein.
  • the combination of the combination of the substrate with the mounted circuit die forms an IC package, such as a memory IC package.
  • a lid is mounted over the side of the substrate on which the circuit die is mounted.
  • the lid is mounted such that the lid at least covers the circuit die.
  • the lid can be removed from the substrate to gain access to the plurality of analog sense points (e.g., for testing or debugging purposes).
  • the lid can be used to dissipate heat.
  • the circuit die can be exposed so that a heat sink can make contact directly to the circuit die.
  • An encapsulant can be used (e.g., like an epoxy or solder mask) to seal and protect the circuit die connections.
  • the combination of the substrate with the mounted circuit die and the mounted lid forms an IC package, such as a memory IC package.

Abstract

Various embodiments described herein provide analog sense points for circuit die, which can form part of an integrated circuit (IC) package and can facilitate measurement of at least a portion of the circuit die using a Kelvin method of measurement.

Description

    TECHNICAL FIELD
  • Embodiments of the disclosure relate generally to voltage measurement and, more specifically, to analog sense points for a circuit die, which can form part of an integrated circuit (IC) package and facilitate measurement of at least a portion of the circuit die using a Kelvin method of measurement.
  • BACKGROUND
  • To facilitate debugging or testing of a manufactured circuit, such as a memory integrated circuit (IC) package, the manufactured circuit can include one or more interfaces that enable measurement of signals or voltages generated by the manufactured circuit using external measuring instruments. For instance, while the manufactured circuit is operating, one or more probes of a measuring instruments can be coupled to an interface of a circuit, which can facilitate measurement of a signal or voltage passing through a portion of the circuit. Additionally, a standard interface, such as a JTAG (Joint Test Action Group) interface, can be used in some instances to provide certain measurements as digital data.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. The drawings, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.
  • FIG. 1 illustrates an example of analog sense points for a circuit die, in accordance with some embodiments of the present disclosure.
  • FIG. 2 illustrates example analog sense points implemented with respect to a substrate of an integrated circuit package, in accordance with some embodiments of the present disclosure.
  • FIG. 3 is a flowchart illustrating an example method for using analog sense points to measure a circuit die, in accordance with some embodiments of the present disclosure.
  • FIG. 4 is a flowchart illustrating an example method for manufacturing a circuit that includes analog sense points to measure a circuit die, in accordance with some embodiments of the present disclosure.
  • DETAILED DESCRIPTION
  • Aspects of the present disclosure are directed to analog sense points for circuit die (or die), which can form part of an integrated circuit (IC) package (e.g., memory circuit die on an IC package) and can facilitate measurement (e.g., voltage measurement) of a portion of the circuit die using a Kelvin method of measuring. In particular, some embodiments provide for one or more analog sense points disposed on a circuit substrate or substrate, such as a printed circuit board (PCB), of an integrated circuit (IC) package, where the one or more analog sense points facilitate a measurement with respect to a die of the IC package that is mounted on the substrate. For instance, an embodiment described herein can be implemented with respect to a circuit die of a memory sub-system. As used herein, a memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and memory module. In general, a host system can utilize a memory sub-system that includes one or more memory components (also hereinafter referred to as “memory devices”). The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.
  • IC packages often rely on digital methods for measuring voltage of the IC packages. Such digital methods usually provide the voltage measurement as digital data via a JTAG (Joint Test Action Group) or similar interface on the IC package. Unfortunately, IC packages suffer from high resistance and inductance, which can result in errors in the measuring provided by the digital methods. Additionally, resolution provided by digital voltage measurement methods can be limited.
  • Kelvin sense points facilitate a Kelvin method for measuring a circuit (e.g., voltage, current, resistance, or impedance thereof) with reduced measurement errors. Generally, a Kelvin method of measurement (also referred to as four-point sensing) is an analog method of measurement, which can be used to measure voltage via four sense points (e.g., probes or electrodes)—one pair of points (also referred to as force points) that is used to measure resistance or impedance (hereafter, resistance/impedance) of a portion of a circuit (e.g., by driving a known current through a portion of a circuit) and another pair of points (also referred to as sense points) that is used to measure voltage of the portion. Additionally, even without using the pair of points for the current, the other pair of points can be used to measure voltage of the portion based on a known or unknown current already flowing through the portion during operation of the circuit. Accordingly, depending on the embodiment, two sense points (e.g., Kelvin sense points) can be used to measure voltage, or four points (e.g., Kelvin sense points) can be used to measure resistance or impedance. Use of a Kelvin method can avoid measurement errors (e.g., voltage measurement errors) that result from inductance or resistance in wires of a circuit. Though Kelvin voltage sense points are useful in measuring a voltage of a circuit, Kelvin voltage sense points are not currently used with respect to IC packages.
  • Aspects of the present disclosure address the deficiencies of conventional methods of measuring voltage of a die of an IC package. According to various embodiments, one or more analog sense points (e.g., pads) are disposed, or embedded, on a top layer (e.g., top side) of a substrate of an IC package, which can facilitate accurate voltage measurement of at least a portion of a circuit die (or die) of the IC package that is mounted on the substrate. In particular, the one or more analog sense points disposed on the top layer of the substrate can facilitate a Kelvin method for measuring a voltage of the die. The one or more analog sense points can serve as Kelvin sense points and facilitate a Kelvin connection between the die and one or more measuring instruments, such as an oscilloscope, a voltmeter, a galvanometer, or a multimeter. For instance, with respect to measuring a portion of a circuit die, the one or more analog sense points comprises one pair of analog sense points that is used to measure voltage of the portion. These two (Kelvin) sense points for measuring voltage has little or no current flowing along its sense lines and, thus, the resistance and inductance do not affect the voltage measurement. In another instance, the one or more analog sense points comprises one pair of analog sense points that is used to measure resistance/impedance of the portion, and another pair of analog sense points that is used to measure voltage of the portion. The first pair of analog sense points can be conductively coupled to outer probe points with respect to the portion, while the second pair of analog sense points can be conductively coupled to inner probe points that are closer with respect to the portion. An example of this is illustrated with respect to FIG. 1 . The substrate can comprise a printed circuit board (PCB) of an IC package. By way of analog sense points described herein, high frequency voltages generated by the die can be measured, such as voltages at 1-10 GHz.
  • For some embodiments, the one or more analog sense points comprise one or more conductive pads (e.g., metal pads) disposed on the substrate. Additionally, an analog sense pad can comprise a solder bump (or bump) disposed on a conductive pad. The die of the IC package can comprise a flip-chip BGA or a wire bond chip with a BGA mounted on the substrate. An analog sense pad can be operatively coupled to the die of the IC package by way of a conductive path (e.g., a wire or a trace) disposed on the substrate.
  • For some embodiments, one or more analog sense points are disposed at or near a periphery or edge of an IC package. In this way, the one or more analog sense points can be disposed where there is less route density than, for example, near a die at a center of the IC package, thereby enabling the one or more analog sense points to have larger dimensions than would otherwise be possible. Some embodiments can be implemented by removing one or more of a package lid, encapsulant, and solder mask of an IC package to expose one or more conductive pads (e.g., metal pads) to be used as one or more analog sense pads.
  • A voltage measurement using top-layer, analog sense points of an embodiment can enable testing and debugging of an IC package, while at least reducing voltage measurement errors. For instance, the top of a substrate outside the circuit die area can be exposed and used for probe points (e.g., with the lid removal description).
  • By embedding the analog sense pads to the top layer of an IC package as described herein, various embodiments can provide measurement of voltage at a circuit die, including high-frequency voltage (e.g., 1-10 GHz), with a higher level of resolution and accuracy than traditional methodologies. Additionally, the analog sense pads described herein can provide measurement of a voltage at a circuit die while reducing or avoiding measurement errors caused by resistance of the IC package or filtering (e.g., of high-frequency voltage) caused by inductance of the IC package. Top layer voltage sense pads of an embodiment can obviate the need for extra bottom side pins for an IC package, which can be expensive and can increase the footprint of the IC package. Additionally, some embodiments can be used as an alternative to using a digital method for measuring voltage of a circuit of an IC package, which can provide a less accurate voltage measurement. The use of some embodiments provides physical access for measuring voltage of a portion of a circuit die (e.g., by placing exposed points on the top of a substrate, regardless of if a lid is used or not), where physical access to a circuit die for such a measurement would be otherwise difficult. Conventional substrate connections at a circuit die are generally not accessible, and lie on top of the substrate and connects between. For conventional substrate connections, there is also no room at the bottom of the package pins since these are reserved (e.g., for important signals and power).
  • Though various embodiments are described herein with respect to pads, it will be understood that for some embodiments the analog sense points can be implemented by different means. Additionally, though various embodiments are described herein with respect to measuring voltage, it will be understood that for some embodiments the analog sense points can be used to measure other aspects of a circuit die, such as resistance/impedance or current.
  • As used herein, a Kelvin method for measuring can also be referred to as four-wire sensing or four-point probes method. Additionally, as used herein, a measuring instrument can comprise a device that measures voltage, current, resistance, impedance, or some combination thereof with respect to a circuit. Examples of measuring instruments can include oscilloscopes, voltmeters, galvanometers, and multimeters.
  • Disclosed herein are some examples of IC packages that include or use voltage sense points as described herein, which can be used to measure voltage using a Kelvin method.
  • FIG. 1 illustrates an example of analog sense points 102, 104, 110, 112 for a circuit die 130, in accordance with some embodiments of the present disclosure. For illustrative purposes, FIG. 1 only presents a simplified representation of analog sense points, on a substrate, that are operatively coupled to a circuit die mounted to the substrate, and excludes additional details that would be typically found in a real-world application of an embodiment.
  • In FIG. 1 , a circuit 100 comprises a substrate 120, a circuit die 130 mounted on a top side of the substrate 120, and analog sense points 102, 104, 110, 112 disposed on the top side of the substrate 120. As shown, the analog sense points 102, 104, 110, 112 are disposed at or near the outer perimeter or edge of the substrate 120, which enables the analog sense points 102, 104, 110, 112 to avoid route congestion at or near the circuit die 130 that would limit the size of the analog sense points 102, 104, 110, 112. Additionally, each of the analog sense points 102, 104, 110, 112 can comprise a conductive pad (e.g., metal pad), which can further have a solder ball (e.g., bump) disposed thereon.
  • For various embodiments, the substrate 120 comprises a printed circuit board. A plurality of connections can be disposed on a bottom side of the substrate 120. For instance, a pin grid array or a ball grid array can be disposed on the bottom side of the substrate 120, which can enable the substrate 120 to operatively couple to a larger circuit (e.g., a larger printed circuit board having a chip socket configured to receive and operatively couple to the substrate 120). By disposing the analog sense points 102, 104, 110, 112 on the top side of the substrate 120, various embodiments can obviate the need for extra connection (e.g., conductive) elements (e.g., pins or balls) disposed on the bottom side of the substrate 120. This can not only reduce the overall cost of manufacturing the circuit 100, but can also avoid having to increase the footprint of the substrate 120.
  • The analog sense points 102, 104, 110, 112 are conductively coupled to a portion 136 of the circuit die 130 by way of conductive paths 132. One or more of the conductive paths 132 can comprise a wire or trace disposed on the top side of the substrate 120. The circuit die 130 can comprise, for example, a flip-chip ball grid array (BGA), where the conductive paths 132 couple the analog sense points 102, 104, 110, 112 to connection elements 134 (e.g., solder ball or bumps) of the ball grid array of the circuit die 130, and where the connection elements 134 couple to corresponding points with respect to portion 136. Though not illustrated, alternatively the circuit die 130 can comprise a wire bond ball grid array (BGA), where wires couple the analog sense points 102, 104, 110, 112 to connection elements of the ball grid array on a top side of the circuit die 130 (e.g., by way another substrate disposed on the ball grid array of the circuit die 130). Additionally, where the circuit die 130 comprises a wire bond BGA and the circuit 100 forms part of an IC package, the top side of the substrate 120 and the circuit die 130 can be covered by an epoxy (or other filling) such that the epoxy (or other filling) is not disposed over the analog sense points 102, 104, 110, 112. For instance, during manufacturing the epoxy can be removed from above the analog sense points 102, 104, 110, 112, thereby providing probe access to the analog sense points 102, 104, 110, 112.
  • The portion 136 can represent one or more components of the circuit die 130. According to various embodiments, the analog sense points 102, 104 are configured to provide a resistance or impedance measurement for the portion 136, and the analog sense points 110, 112 are configured to provide a voltage measurement across the portion 136. As shown, the analog sense points 110, 112 are coupled closer on the conductive path of the portion 136 than the analog sense points 102, 104. In view of this, one or more measuring instruments (e.g., probes thereof) can couple to the analog sense points 102, 104, 110, 112 to form a Kelvin connection, which can enable the one or more measuring instruments to measure voltage across the portion 136 using a Kelvin method. Accordingly, in the context of the Kelvin method of measurement, the analog sense points 102, 104 can represent force points or probes, and the analog sense points 110, 112 can represent sense points or probes. According to some embodiments, by forming a Kelvin connection with the analog sense points 102, 104, 110, 112, the one or more measuring instruments can measure a high-frequency voltage (e.g., 1-10 Ghz) at the circuit die 130 (across the portion 136), can do so with a higher resolution than traditional technologies, and can do so while avoiding measurement errors (e.g., caused by resistance or inductance caused by IC packaging, etc.).
  • FIG. 2 illustrates example analog sense points implemented with respect to a substrate 200 of an IC package, in accordance with some embodiments of the present disclosure. In FIG. 2 , a top side of the substrate 200 includes analog sense pads 210, 212, 214, 216, which are conductively coupled to the center portion 220 of the substrate 200. According to various embodiments, the center portion 220 of the substrate 200 corresponds to a location on the substrate 200 where a circuit die would mount, and operatively couple, to the substrate 200. The traces disposed on the substrate 200 can couple to connection elements of a circuit die mounted to the substrate 200. Additionally, at least some of those traces can couple one or more of the analog sense pads 210, 212, 214, 216 to corresponding connection elements of the circuit die, which can facilitate one or more Kelvin connections with one or more portions of the circuit die as described herein.
  • FIG. 3 is a flowchart illustrating an example method 300 for using analog sense points to measure a circuit die, in accordance with some embodiments of the present disclosure. For instance, the method 300 can be performed with respect to the circuit 100 of FIG. 1 or with respect to the substrate 200 of FIG. 2 . Depending on the embodiment, the method 300 can be performed during testing or debugging of a circuit, or more specifically, the circuit die coupled to the analog sense points.
  • Initially, at operation 302, a user can remove a package lid, encapsulant, a solder mask, or some combination thereof from a circuit (e.g., 100), which can expose analog sense points (e.g., 102, 104, 110, 112) of the circuit (e.g., 100) and render them accessible by probes of one or more measuring instruments. Operation 302 can be performed where the circuit (e.g., 100) forms part of a IC package.
  • At operation 304, a user (e.g., electrical engineer or technician) couples one or more measuring instruments to a plurality of analog sense points (e.g., 102, 104, 110, 112) of a circuit (e.g., 100) comprising the analog sense points and a circuit die (e.g., 130). For various embodiments, the circuit (e.g., 100) comprises a substrate (e.g., 120) having a top side, and the circuit die (e.g., 130) is mounted to the top side of the substrate (e.g., 120). Additionally, the analog sense points (e.g., 102, 104, 110, 112) are disposed on the top side of the substrate (e.g., 120), and the analog sense points are operatively coupled to the circuit die (e.g., 130) such that the analog sense points are configured to provide a voltage measurement for a portion (e.g., 136) of the circuit die (e.g., 130). According to various embodiments, the analog sense points (e.g., 102, 104, 110, 112) comprise a first sub-plurality (e.g., pair) of analog sense points (e.g., 110, 112) for measuring voltage of the portion (e.g., 136) and a second sub-plurality (e.g., pair) of analog sense points (e.g., 102, 104) for measuring resistance or impedance of the portion (e.g., 136). In view of this, the one or more measuring instruments can be coupled to the analog sense points (e.g., 102, 104, 110, 112) such that voltage probes of the one or more measuring instruments are coupled to the first sub-plurality of analog sense points (e.g., 110, 112), and current/resistance/impedance probes of the one or more measuring instruments are coupled to the second sub-plurality of analog sense points (e.g., 102, 104). This can represent the one or more measurement instruments forming a Kelvin connection with respect to the portion (e.g., 136) of the circuit die (e.g., 130) by way of the analog sense points (e.g., 102, 104, 110, 112).
  • For some embodiments, voltage of the portion (e.g., 136) is measured by the first sub-plurality of analog sense points (e.g., 110, 112). Additionally, for some embodiments, resistance/impedance of the portion (e.g., 136) is measured by driving a known current the second sub-plurality of analog sense points (e.g., 102, 104), measuring voltage of the portion (e.g., 136) using the first sub-plurality of analog sense points (e.g., 110, 112), and determining the resistance or impedance of the portion (e.g., 136) using the known current and the measured voltage (e.g., resistance equals the measured voltage divided by the known current (R=V/I)). Resistance can be without any time varying signal (e.g., direct current(DC)), and impedance can be with a time varying signal (e.g., alternating current (AC)), where impedance includes resistance plus the effects of inductance and capacitance.
  • Eventually, at operation 306, a voltage of the portion (e.g., 136) is measured by the one or more measuring instruments using a Kelvin method of measurement. The one or more measuring instruments used can include, without limitation, an oscilloscope, a voltmeter, a galvanometer, or a multimeter.
  • FIG. 4 is a flowchart illustrating an example method 400 for manufacturing a circuit that includes analog sense points to measure a circuit die, in accordance with some embodiments of the present disclosure. For example, the method 400 can be used to manufacture a circuit similar to the circuit 100 of FIG. 1 or a substrate similar to the substrate 200 of FIG. 2 .
  • At operation 402, a circuit die is manufactured that includes a plurality of external connection elements (e.g., pins, bumps, or solder balls) that are configured to provide a Kelvin connection with a portion (e.g., internal component or electrical path) of the circuit die. For instance, where the circuit die comprises a ball grid array (BGA) as part of its external connection elements, at least two connection elements (e.g., four connection elements of 134 of FIG. 1 ) of the ball grid array (e.g., bumps or solder balls) can be configured to provide a Kelvin connection with the portion (e.g., 136 of FIG. 1 ). In particular, the circuit die can include internal routing or wiring that operatively couples the at least four connection elements to the portion of the circuit die such that when one or more measuring instruments are coupled to the at least two connections (by way of analog sense pads on the substrate), a Kelvin connection is formed between the one or more measuring instruments and the portion of the circuit die. Additionally, the external connection elements (e.g., at least four connection elements of the ball grid array) can be positioned such that once the circuit die is mounted to a substrate as described herein, those external connection elements operatively couple to conductive paths (e.g., wires or traces) on the substrate that operatively couple to analog sense pads on the substrate.
  • During operation 404, a substrate (e.g., 120 of FIG. 1 ) of a circuit is manufactured, where the substrate comprises a plurality of analog sense points (e.g., 102, 104, 110, 112 of FIG. 1 ) disposed on a side of the substrate, and a plurality of conductive paths (e.g., 132 of FIG. 1 ) operatively coupling the plurality of analog sense points to a (mount) location, on the side of the substrate, configured to receive a circuit die (e.g., location on the substrate 120 that receives 134 of FIG. 1 ). Depending on the embodiment, the conductive paths can comprise wires or traces disposed on the substrate.
  • Thereafter, at operation 406, the circuit die manufactured at operation 402, is mounted to the mount location on the substrate such that the circuit die is operatively coupled to the plurality of analog sense points (e.g., 102, 104, 110, 112 of FIG. 1 ) by way of the plurality of conductive paths (e.g., 132 of FIG. 1 ). In this way, the plurality of analog sense points can provide a voltage measurement for the portion (e.g., 136 of FIG. 1 ) of the circuit die, and can do so by way of a Kelvin connection as described herein. According to some embodiments, the combination of the combination of the substrate with the mounted circuit die forms an IC package, such as a memory IC package.
  • Eventually, at operation 408, a lid is mounted over the side of the substrate on which the circuit die is mounted. According to various embodiments, the lid is mounted such that the lid at least covers the circuit die. For some embodiments, where the lid is mounted such that lid covers the circuit die and one or more of the plurality of analog sense points, the lid can be removed from the substrate to gain access to the plurality of analog sense points (e.g., for testing or debugging purposes). Generally, the lid can be used to dissipate heat. Additionally, the circuit die can be exposed so that a heat sink can make contact directly to the circuit die. An encapsulant can be used (e.g., like an epoxy or solder mask) to seal and protect the circuit die connections. According to some embodiments, the combination of the substrate with the mounted circuit die and the mounted lid forms an IC package, such as a memory IC package.
  • In the foregoing specification, embodiments of the disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications can be made thereto without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims (20)

What is claimed is:
1. A circuit comprising:
a substrate having a top side;
a circuit die mounted to the top side of the substrate; and
a plurality of analog sense points disposed on the top side of the substrate, the plurality of analog sense points being operatively coupled to the circuit die such that the plurality of analog sense points is configured to provide a voltage measurement for a portion of the circuit die.
2. The circuit of claim 1, wherein the plurality of analog sense points is configured to provide the voltage measurement using a Kelvin method of measurement.
3. The circuit of claim 2, wherein the plurality of analog sense points comprises a sub-plurality of analog sense points, and wherein the sub-plurality of analog sense points comprises a first pair of analog sense points for measuring voltage of the portion and a second pair of analog sense points for measuring resistance or impedance of the portion.
4. The circuit of claim 1, wherein the circuit die comprises a flip-chip ball grid array (BGA).
5. The circuit of claim 1, wherein the circuit die comprises a wire bond ball grid array (B GA), and each analog sense point of the plurality of analog sense points is operatively coupled to the wire bond ball grid array by way of a wire to a top side of the circuit die.
6. The circuit of claim 5, wherein the circuit forms part of an integrated circuit (IC) package, and the top side and the wire bond ball grid array is covered by an epoxy such that the epoxy is not disposed over the plurality of analog sense points.
7. The circuit of claim 1, wherein the circuit forms part of an integrated circuit package, and the substrate comprises a printed circuit board.
8. The circuit of claim 1, wherein the plurality of analog sense points is disposed at or near an outer perimeter of the substrate.
9. The circuit of claim 1, wherein one of a pin grid array or a ball grid array is disposed on a bottom side of the substrate.
10. The circuit of claim 1, wherein each of one or more analog sense points comprises a conductive pad.
11. An integrated circuit package comprising:
a printed circuit board having a top side and a bottom side, the bottom side having one of a pin grid array or a ball grid array disposed thereon;
a circuit die mounted to the top side of the printed circuit board; and
a plurality of analog sense pads disposed on the top side of the printed circuit board, the plurality of analog sense pads being operatively coupled to the circuit die such that the plurality of analog sense pads is configured to provide a voltage measurement for a portion of the circuit die.
12. The integrated circuit package of claim 11, wherein the plurality of analog sense pads is configured to provide the voltage measurement using a Kelvin method of measurement.
13. The integrated circuit package of claim 12, wherein the plurality of analog sense pads comprises a sub-plurality of analog sense pads, and wherein the sub-plurality of analog sense pads comprises a first pair of analog sense pads for measuring voltage of the portion and a second pair of analog sense pads for measuring resistance or impedance of the portion.
14. The integrated circuit package of claim 11, wherein the circuit die comprises a flip-chip ball grid array (B GA).
15. The integrated circuit package of claim 11, wherein the circuit die comprises a wire bond ball grid array (BGA), and each analog sense pad of the plurality of analog sense pads is operatively coupled to the wire bond ball grid array by way of a wire to a top side of the circuit die.
16. The integrated circuit package of claim 15, wherein the top side of the printed circuit board and the circuit die are covered by an epoxy such that the epoxy is not disposed over the plurality of analog sense pads.
17. The integrated circuit package of claim 11, wherein the plurality of analog sense pads is disposed at or near an outer perimeter of the printed circuit board.
18. A method comprising:
manufacturing a circuit substrate that comprises:
a plurality of analog sense points disposed on a side of the circuit substrate; and
a plurality of conductive paths operatively coupling the plurality of analog sense points to a location, on the side of the circuit substrate, configured to receive a circuit die; and
mounting the circuit die to the location such that the circuit die is operatively coupled to the plurality of analog sense points by way of the plurality of conductive paths, the plurality of analog sense points being configured to provide a voltage measurement for a portion of the circuit die.
19. The method of claim 18, comprising:
mounting a lid over the side of the circuit substrate such that the lid at least covers the circuit die.
20. The method of claim 18, wherein the circuit die comprises a ball grid array, the method comprising:
manufacturing the circuit die to include at least two connection elements of a ball grid array that are configured to provide a Kelvin connection with the portion of the circuit die, the at least two connection elements being positioned in the ball grid array to operatively couple to at least two of the analog sense points of the plurality of conductive paths when the circuit die is mounted to the circuit substrate.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5334857A (en) * 1992-04-06 1994-08-02 Motorola, Inc. Semiconductor device with test-only contacts and method for making the same
US5838161A (en) * 1996-05-01 1998-11-17 Micron Technology, Inc. Semiconductor interconnect having test structures for evaluating electrical characteristics of the interconnect
US6297653B1 (en) * 1999-06-28 2001-10-02 Micron Technology, Inc. Interconnect and carrier with resistivity measuring contacts for testing semiconductor components
US20140266283A1 (en) * 2013-03-13 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-Wafer Process Control Monitoring for Chip-on-Wafer-on-Substrate Packages

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5334857A (en) * 1992-04-06 1994-08-02 Motorola, Inc. Semiconductor device with test-only contacts and method for making the same
US5838161A (en) * 1996-05-01 1998-11-17 Micron Technology, Inc. Semiconductor interconnect having test structures for evaluating electrical characteristics of the interconnect
US6297653B1 (en) * 1999-06-28 2001-10-02 Micron Technology, Inc. Interconnect and carrier with resistivity measuring contacts for testing semiconductor components
US20140266283A1 (en) * 2013-03-13 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-Wafer Process Control Monitoring for Chip-on-Wafer-on-Substrate Packages

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