JPS6347273B2 - - Google Patents
Info
- Publication number
- JPS6347273B2 JPS6347273B2 JP20480481A JP20480481A JPS6347273B2 JP S6347273 B2 JPS6347273 B2 JP S6347273B2 JP 20480481 A JP20480481 A JP 20480481A JP 20480481 A JP20480481 A JP 20480481A JP S6347273 B2 JPS6347273 B2 JP S6347273B2
- Authority
- JP
- Japan
- Prior art keywords
- terminals
- integrated circuit
- circuit
- probe
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims 2
- 239000000523 sample Substances 0.000 description 9
- 238000000605 extraction Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は集積回路に関し、特にDIP型集積回路
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to integrated circuits, and more particularly to DIP type integrated circuits.
従来、DIP型集積回路は直方体に近いパツケー
ジの長手方向の側面に外部接続用の端子の列が２
列並べられた構造を有しており、印刷回路基板等
への実装に適する構造になつている。 Conventionally, DIP integrated circuits have two rows of terminals for external connections on the longitudinal side of a nearly rectangular parallelepiped package.
It has a structure that is arranged in rows, and is suitable for mounting on a printed circuit board or the like.
最近の電子装置の小型化に伴い、印刷回路基板
への実装密度が高くなつてきている。集積回路を
実装した印刷回路基板の試験にはICクリツプ方
式のインサーキツト・テスタが用いられている
が、集積回路の高密度実装化に伴い集積回路間の
隙間が狭くなり、ICクリツプが入りにくくなり
被試験集積回路に接続できなくなるという欠点が
あつた。 With the recent miniaturization of electronic devices, the packaging density on printed circuit boards has become higher. IC clip type insert circuit testers are used to test printed circuit boards with integrated circuits mounted on them, but as integrated circuits become more densely packaged, the gaps between integrated circuits become narrower, making it difficult for IC clips to enter. The drawback was that it could not be connected to the integrated circuit under test.
本発明は上記欠点を除去し、印刷回路基板に高
密度実装してもインサーキツト・テスタが支障な
く使用でき、回路試験ができる構造を有する集積
回路を提供するものである。 The present invention eliminates the above-mentioned drawbacks and provides an integrated circuit having a structure that allows the use of an in-circuit tester without any trouble even when the integrated circuit is mounted on a printed circuit board at high density and allows circuit testing.
本発明の集積回路は、パツケージの側面と上面
とに外部接続用の端子を設け、前記側面の端子と
上面の端子とが１対１対応で電気的に接続されて
構成される。 The integrated circuit of the present invention is configured such that external connection terminals are provided on the side surface and the top surface of the package, and the terminals on the side surface and the terminals on the top surface are electrically connected in a one-to-one correspondence.
本発明の実施例について図面を用いて説明す
る。 Embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の一部切欠き斜視図
である。 FIG. 1 is a partially cutaway perspective view of an embodiment of the present invention.
集積回路１０ののパツケージの長手側の側面１
１，１１′にそれぞれ外部引出し用の端子１３，
１３′の列が設けられている。パツケージの上面
１２にも端子１４，１４′の列が設けられる。端
子１３と１４、１３′と１４′とはそれぞれ１対１
対応でパツケージ内で電気的に接続される。 Longitudinal side 1 of the package of the integrated circuit 10
1 and 11' are terminals 13 for external extraction, respectively.
There are 13' rows. The top surface 12 of the package is also provided with a row of terminals 14, 14'. Terminals 13 and 14, 13' and 14' are 1:1, respectively.
It is electrically connected within the package.
第２図は第１図に示す一実施例の試験を行うと
きに使用されるインサーキツト・テスタのプロー
ブの一例の斜視図である。 FIG. 2 is a perspective view of an example of the probe of the in-circuit tester used when testing the embodiment shown in FIG. 1.
プローブ２０はほぼ直方体のパツケージの一面
にプローブピン２１，２１′の列を有し、反対面
にフラツト・ケーブル２２を取付け、プローブピ
ン２１，２１′と電気的に接続せしめる。プロー
ブピン２１，２１′は第１図の集積回路１０の上
面の端子１４，１４′の列と同じ位置に配列され
ている。従つて、プローブピン２１，２１′を端
子４，１４′に上から接触せしめることにより集
積回路１０の試験を行うことができる。このよう
に集積回路の上面に外部接続用の端子を設けてお
くと、集積回路１０の側面の端子１３，１３′と
ICクリツプとの接触をとる必要がなくなり、集
積回路の印刷回路基板への高密度実装が可能とな
る。 The probe 20 has a row of probe pins 21, 21' on one side of a substantially rectangular parallelepiped package, and a flat cable 22 is attached to the opposite side and electrically connected to the probe pins 21, 21'. The probe pins 21, 21' are arranged at the same positions as the rows of terminals 14, 14' on the top surface of the integrated circuit 10 in FIG. Therefore, the integrated circuit 10 can be tested by bringing the probe pins 21, 21' into contact with the terminals 4, 14' from above. By providing external connection terminals on the top surface of the integrated circuit in this way, the terminals 13 and 13' on the side surface of the integrated circuit 10 and
This eliminates the need for contact with IC clips, allowing high-density mounting of integrated circuits on printed circuit boards.
以上詳細に説明したように、本発明によれば、
印刷回路基板に高密度実装してもインサーキツ
ト・テスタによる回路試験が容易にできる集積回
路が得られるのでその効果は大きい。 As explained in detail above, according to the present invention,
This is highly effective because it provides an integrated circuit that can be easily tested using an in-circuit tester even if it is mounted on a printed circuit board at high density.
第１図は本発明の一実施例の一部切欠き斜視
図、第２図は第１図に示す一実施例の試験を行う
ときに使用されるインサーキツト・テスタのプロ
ーブの一例の斜視図である。
１０…集積回路、１１，１１′…側面、１２…
上面、１３，１３′…端子、１４，１４′…端子、
２０…プローブ、２１，２１′…プローブピン、
２２…フラツト・ケーブル。
FIG. 1 is a partially cutaway perspective view of an embodiment of the present invention, and FIG. 2 is a perspective view of an example of the probe of an in-circuit tester used when testing the embodiment shown in FIG. be. 10... integrated circuit, 11, 11'... side surface, 12...
Top surface, 13, 13'... terminal, 14, 14'... terminal,
20...probe, 21,21'...probe pin,
22...Flat cable.
Claims (1)
たパツケージの側面と上面とに外部接続用の端子
が設けられ、前記側面の端子と上面の端子とが１
対１対応で電気的に接続され、かつ前記半導体チ
ツプの電極が前記端子に電気的に接続されている
ことを特徴とする集積回路。1. Terminals for external connection are provided on the side and top surfaces of a package housing a semiconductor chip on which a circuit is formed, and the terminals on the side and top surfaces are connected to 1.
An integrated circuit characterized in that the integrated circuit is electrically connected in a pair-to-one correspondence, and the electrodes of the semiconductor chip are electrically connected to the terminals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20480481A JPS58106854A (en) | 1981-12-18 | 1981-12-18 | Integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20480481A JPS58106854A (en) | 1981-12-18 | 1981-12-18 | Integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58106854A JPS58106854A (en) | 1983-06-25 |
| JPS6347273B2 true JPS6347273B2 (en) | 1988-09-21 |
Family
ID=16496634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20480481A Granted JPS58106854A (en) | 1981-12-18 | 1981-12-18 | Integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58106854A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58106950U (en) * | 1982-01-13 | 1983-07-21 | 富士通株式会社 | Semiconductor device package |
| JPS6034047A (en) * | 1983-08-05 | 1985-02-21 | Nec Corp | Integrated circuit package |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5025466U (en) * | 1973-06-30 | 1975-03-24 | ||
| JPS5476675U (en) * | 1977-11-10 | 1979-05-31 | ||
| JPS6020932Y2 (en) * | 1979-02-05 | 1985-06-22 | 日本電気株式会社 | semiconductor equipment |
| JPS59133B2 (en) * | 1979-12-21 | 1984-01-05 | 富士通株式会社 | Multi-chip semiconductor package |
| JPS6221016Y2 (en) * | 1980-11-14 | 1987-05-28 |
-
1981
- 1981-12-18 JP JP20480481A patent/JPS58106854A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58106854A (en) | 1983-06-25 |
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