CA1273130A - Test point adapter for chip carrier sockets - Google Patents
Test point adapter for chip carrier socketsInfo
- Publication number
- CA1273130A CA1273130A CA000539718A CA539718A CA1273130A CA 1273130 A CA1273130 A CA 1273130A CA 000539718 A CA000539718 A CA 000539718A CA 539718 A CA539718 A CA 539718A CA 1273130 A CA1273130 A CA 1273130A
- Authority
- CA
- Canada
- Prior art keywords
- terminal
- pin
- chip carrier
- test point
- terminal means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
- G01R1/0416—Connectors, terminals
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Measuring Leads Or Probes (AREA)
- Tests Of Electronic Circuits (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Multi-Conductor Connections (AREA)
Abstract
TEST POINT ADAPTOR FOR CHIP CARRIER SOCKETS
ABSTRACT OF THE INVENTION
This arrangement provides for attaching test or probe leads for such instruments as a logic analyzer to a leaded chip carrier. This arrangement provides for terminating each chip carrier lead to a metallic post upon which a logic probe or other test apparatus may be mechanically attached to make electrical connection. Since leaded chip carriers have their contact leads closely spaced, this arrangement expands this distance between leads to a suitable distance for connecting test probes. In this manner, the semiconductor chip may be functionally tested as part of a circuit on a printed wiring card.
ABSTRACT OF THE INVENTION
This arrangement provides for attaching test or probe leads for such instruments as a logic analyzer to a leaded chip carrier. This arrangement provides for terminating each chip carrier lead to a metallic post upon which a logic probe or other test apparatus may be mechanically attached to make electrical connection. Since leaded chip carriers have their contact leads closely spaced, this arrangement expands this distance between leads to a suitable distance for connecting test probes. In this manner, the semiconductor chip may be functionally tested as part of a circuit on a printed wiring card.
Description
1273~
TEST POINT A~APTER FOR CHIP CARRIER SOCKETS
BACKGROUND OF THE INVENTION
This invention pertains to electronic testing of socket mounted semiconductor chips and more particularly to electronic testing of chips in sockets with a large number of leads which are closely positioned.
One packaging type for integrated circuits is a leaded chip carrier (LCC) type. The LCC has leads on all four sides with spacing in between of 0.050 inch. Sockets for mounting a chip carrier to a printed wiring card do not provide any means for attaching testing apparatus leads. The chip carrier itself does not allow for physically attaching any test probe apparatus. Most test leads, such as logic analyzer probes, require 0.100 inch spacings between test points.
Another type of integrated circuit package is the dual in-line package (DIP). The DIP chips have leads on only two sides with pins spaced at 0.100 inch. Commercially available DIP clips (like clothes pins) may be clipped directly onto the chip leads in order to perform testing. These clips provide relatively long pins to which a logic probe may be attached. No clip type device can be adapted to a four sided LCC package when the LCC package is mounted in a suitable socket.
SUMMARY OF THE INVENTION
A test point adaptor permits connection of a test probe to the leads of a semiconductor chip which is mounted in a leaded chip carrier. Electrical connection may not be made directly to the semiconductor chip while it is mounted in the leaded chip carrier.
The test point adaptor includes a circuit board whlch has a number of conductive paths. Each conductive path is connected between an inner point of the circuit board and an outer point of the circuit board.
A first connector array is mounted to the circuit board. The first connector array has a number of terminal pins.
Each of the terminal pins is connected to a corresponding inner 3L~7 3 l~O
polnt of a particular conductive pa~h. ~he first connector arra~
is also connected to the leaded chip carrier which contains the semicon~uctor chip.
~he test point adaptor also has a second connector array. The second connector array is mounted to the circuit board. me second connector array has a nNmber of terminal pins, each of which is connected to a corresponding outer point of a corresponding conductive path.
The test probe may now be connected to any of the termlnal pins of the second connector to obtain electrical aocess for testing the semiconductor chip which is mcunted in the leaded chip carrier.
A ~RIEF DESCRIPlION OF TEIE I~1INGS
Figure 1 is an assembly drawing of test point adaptor embodying the principles of operation of the present invention.
Figure 2 is a layout of the foil paths of the printed wiring card of Figure l.
DESCRIPqION OF THE PRSFERRED EMBODIMENT
Referring to Figures l and 2, a chip carrier 20 is shown mcNnted on a test point adaptor 100. The printed wiring card 10 is an approxImately tw~ (2) inch square. m e chip carrier 20 is approximately one and three-sixteenths inch square. m ere are seventeen (17) connection points on each side of the chip carrier square. The printed wiring card 10 allows electrical contact to be made along the two inch square side.
The printed wiring ¢ard 10 has foil paths 30 which allaw widening of the distanoe between conductors 40 on the chip carrier 20 from 0.050 inch to 0.100 inch required for attaching a lagic prcbe. The printed wiring card 10 includes a plurality of foil paths 30 connecting respective inner foil pads 32 to auter foil pads 34. Each foil pad 32 and 34, includes a centrally lacatad hole (nok shown) e#tendin~ thru the printed wiring card 10. A
plurality of terminal strip devioes 50 are installed on the printed wiring oard 10. Each terminal strip devioe includes a row of pin receiving portions or sockets 51 and a row of pins 52.
Each socket 51 is integrally joined to an associated terminal pin 52 which extend outward directly opposite fram its associated socket 51.
~ ~7~
Each pin 52 is arranged to be inserted through a respective drilled hole of each mner foil pad 32. me inner foil pads 32 are grcuped into tT~o side-by-side rows on each side of a square perimster. me inner row accepts an eight pin termm al strip device 50 and the outer row of each side of the square contains a nine pin terminal strip device 50. m ese pin strips are manufactured by Samtec and are part no. SS-101-G-~.
Electrical connection is made between the pins 52 and the foil pads 32 by soldering. This soldering operation also provides for mechanical stability of the terminal strip devices 50 and the printed wiring card 10.
me outer foil pads 34 are arranged into four linear groups with each group extending longitudinally along a respective perimeter edge of wiring card 10. Terminal strip devices 60 having upper and lower pins 61 are mounted to the printed wiring card 10 by having the lower pins 61 (not shown) inserted through a respective and associated drilled hole on the top of wiring card 10, thereby, allowing each lower pin 61 to extend thru the circuit card and exit from an associated foil pad 34 on the bottom of the
TEST POINT A~APTER FOR CHIP CARRIER SOCKETS
BACKGROUND OF THE INVENTION
This invention pertains to electronic testing of socket mounted semiconductor chips and more particularly to electronic testing of chips in sockets with a large number of leads which are closely positioned.
One packaging type for integrated circuits is a leaded chip carrier (LCC) type. The LCC has leads on all four sides with spacing in between of 0.050 inch. Sockets for mounting a chip carrier to a printed wiring card do not provide any means for attaching testing apparatus leads. The chip carrier itself does not allow for physically attaching any test probe apparatus. Most test leads, such as logic analyzer probes, require 0.100 inch spacings between test points.
Another type of integrated circuit package is the dual in-line package (DIP). The DIP chips have leads on only two sides with pins spaced at 0.100 inch. Commercially available DIP clips (like clothes pins) may be clipped directly onto the chip leads in order to perform testing. These clips provide relatively long pins to which a logic probe may be attached. No clip type device can be adapted to a four sided LCC package when the LCC package is mounted in a suitable socket.
SUMMARY OF THE INVENTION
A test point adaptor permits connection of a test probe to the leads of a semiconductor chip which is mounted in a leaded chip carrier. Electrical connection may not be made directly to the semiconductor chip while it is mounted in the leaded chip carrier.
The test point adaptor includes a circuit board whlch has a number of conductive paths. Each conductive path is connected between an inner point of the circuit board and an outer point of the circuit board.
A first connector array is mounted to the circuit board. The first connector array has a number of terminal pins.
Each of the terminal pins is connected to a corresponding inner 3L~7 3 l~O
polnt of a particular conductive pa~h. ~he first connector arra~
is also connected to the leaded chip carrier which contains the semicon~uctor chip.
~he test point adaptor also has a second connector array. The second connector array is mounted to the circuit board. me second connector array has a nNmber of terminal pins, each of which is connected to a corresponding outer point of a corresponding conductive path.
The test probe may now be connected to any of the termlnal pins of the second connector to obtain electrical aocess for testing the semiconductor chip which is mcunted in the leaded chip carrier.
A ~RIEF DESCRIPlION OF TEIE I~1INGS
Figure 1 is an assembly drawing of test point adaptor embodying the principles of operation of the present invention.
Figure 2 is a layout of the foil paths of the printed wiring card of Figure l.
DESCRIPqION OF THE PRSFERRED EMBODIMENT
Referring to Figures l and 2, a chip carrier 20 is shown mcNnted on a test point adaptor 100. The printed wiring card 10 is an approxImately tw~ (2) inch square. m e chip carrier 20 is approximately one and three-sixteenths inch square. m ere are seventeen (17) connection points on each side of the chip carrier square. The printed wiring card 10 allows electrical contact to be made along the two inch square side.
The printed wiring ¢ard 10 has foil paths 30 which allaw widening of the distanoe between conductors 40 on the chip carrier 20 from 0.050 inch to 0.100 inch required for attaching a lagic prcbe. The printed wiring card 10 includes a plurality of foil paths 30 connecting respective inner foil pads 32 to auter foil pads 34. Each foil pad 32 and 34, includes a centrally lacatad hole (nok shown) e#tendin~ thru the printed wiring card 10. A
plurality of terminal strip devioes 50 are installed on the printed wiring oard 10. Each terminal strip devioe includes a row of pin receiving portions or sockets 51 and a row of pins 52.
Each socket 51 is integrally joined to an associated terminal pin 52 which extend outward directly opposite fram its associated socket 51.
~ ~7~
Each pin 52 is arranged to be inserted through a respective drilled hole of each mner foil pad 32. me inner foil pads 32 are grcuped into tT~o side-by-side rows on each side of a square perimster. me inner row accepts an eight pin termm al strip device 50 and the outer row of each side of the square contains a nine pin terminal strip device 50. m ese pin strips are manufactured by Samtec and are part no. SS-101-G-~.
Electrical connection is made between the pins 52 and the foil pads 32 by soldering. This soldering operation also provides for mechanical stability of the terminal strip devices 50 and the printed wiring card 10.
me outer foil pads 34 are arranged into four linear groups with each group extending longitudinally along a respective perimeter edge of wiring card 10. Terminal strip devices 60 having upper and lower pins 61 are mounted to the printed wiring card 10 by having the lower pins 61 (not shown) inserted through a respective and associated drilled hole on the top of wiring card 10, thereby, allowing each lower pin 61 to extend thru the circuit card and exit from an associated foil pad 34 on the bottom of the
2~ circuit card. m ese large t~rminal strip pins are part no.
TSW-136-070-G-S manufactured by Samtec. A strip of these terminal strip devices 60 include seventeen pins (17). me upper pins 61 are a sufficient distance apart (0.100 inch) to permit the connection of test probes to test the functiQns of the semiconductor chip (not shown) contained in the chip carrier 2C.
A test prQbe such as a part no. 010-6451-00 may be connected to upper pins 61. me test probe mentioned above is Don=f:cturei by the Tektronics Corporation and may be plugged into a logic analyzer model no. 7D01 also manufactured by Tektronics.
me lower pins 61 of the terminal strip device 60 are soldered to a respective foil pad 34. This soldering also provides for a stable connection of the termin~l strip devices 60 to the printed wiring card.
Next, the chip ~rrier 20 may be inserted into the terminal strip devices 50. me integrated circuit chip (not shown) may have keen previcusly inserted into the chip carrier 20 or chip carrier 20 may be removed and another chip fitted into the chip carrier 20. The pins 22 of the chip carrier 20 must be ' 3 ~7~
carefully aligned with the female opening of the terminal strip devices 50, so that the chip carrier pins 22 do not flex or bend and are all evenly seated and the chip carrier 20 urged downward inserting each pin 22 into a respective and associated socket 51 to make sufficient electrical contact.
Lastly, a third set of terminal strip devices 70 identical to termlnal strip devices 50, have their sockets 71 connected to a respective and associated pin 52 of terminal strip devices 50. The pins 72 of terminal strip devices 70 are part no.
SS-lol-G-2 and are also manufactured by Samtec. me pins 72 of terminal strip devices 70 extend fram the bottam of printed wiring card 10 and facilitate the mountLng of the completed adaptor assembly 100 containing the chip carrier 20 to a master printed wiring card (not shown), so that the resulting master printed wiring card assembly may be tested and the semiconductor chips easily inserted, remcved or changed.
Although the preferred embodiment of the invention has been illustrated, and that form descr;hc~ in detail, it will be readily apparent to those skilled in the art that various modifications may be made therein without departing from the spirit of the invention or from the scope of the appended claims.
TSW-136-070-G-S manufactured by Samtec. A strip of these terminal strip devices 60 include seventeen pins (17). me upper pins 61 are a sufficient distance apart (0.100 inch) to permit the connection of test probes to test the functiQns of the semiconductor chip (not shown) contained in the chip carrier 2C.
A test prQbe such as a part no. 010-6451-00 may be connected to upper pins 61. me test probe mentioned above is Don=f:cturei by the Tektronics Corporation and may be plugged into a logic analyzer model no. 7D01 also manufactured by Tektronics.
me lower pins 61 of the terminal strip device 60 are soldered to a respective foil pad 34. This soldering also provides for a stable connection of the termin~l strip devices 60 to the printed wiring card.
Next, the chip ~rrier 20 may be inserted into the terminal strip devices 50. me integrated circuit chip (not shown) may have keen previcusly inserted into the chip carrier 20 or chip carrier 20 may be removed and another chip fitted into the chip carrier 20. The pins 22 of the chip carrier 20 must be ' 3 ~7~
carefully aligned with the female opening of the terminal strip devices 50, so that the chip carrier pins 22 do not flex or bend and are all evenly seated and the chip carrier 20 urged downward inserting each pin 22 into a respective and associated socket 51 to make sufficient electrical contact.
Lastly, a third set of terminal strip devices 70 identical to termlnal strip devices 50, have their sockets 71 connected to a respective and associated pin 52 of terminal strip devices 50. The pins 72 of terminal strip devices 70 are part no.
SS-lol-G-2 and are also manufactured by Samtec. me pins 72 of terminal strip devices 70 extend fram the bottam of printed wiring card 10 and facilitate the mountLng of the completed adaptor assembly 100 containing the chip carrier 20 to a master printed wiring card (not shown), so that the resulting master printed wiring card assembly may be tested and the semiconductor chips easily inserted, remcved or changed.
Although the preferred embodiment of the invention has been illustrated, and that form descr;hc~ in detail, it will be readily apparent to those skilled in the art that various modifications may be made therein without departing from the spirit of the invention or from the scope of the appended claims.
Claims (7)
1. A test point adaptor for permitting an electrical connection of a test probe apparatus to a semiconductor chip mounted in a semiconductor chip carrier, said chip carrier including a plurality of connecting pins electrically connected to said semiconductor chip extending from said chip carrier, said test point adaptor comprising:
a circuit board having a pluralitiv of conductive foil paths, each conductive foil path connecting a corresponding inner foil pad to a corresponding outer foil pad;
first terminal means connected to said circuit board, said first terminal means including a plurality of electrically conductive pin members, each pin member electrically connected to a corresponding inner foil pad;
said first terminal means further including a plurality of electrically conductive pin accepting members, each pin member electrically connected to an associated first terminal means pin member and each pin accepting member is arranged to accept a respective and associated chip carrier connecting pin, therein, connecting said circuit board and said foil paths to said chip carrier with said semiconductor chip: and second terminal means connected to said circuit board, said second terminal means including a plurality of electrically conductive pin members, each of said second terminal means pin members connected to a corresponding outer foil pad of said circuit card, said second terminal means pin members providing for selective electrical connection of said test probe apparatus to said semiconductor chip in said leaded chip carrier.
a circuit board having a pluralitiv of conductive foil paths, each conductive foil path connecting a corresponding inner foil pad to a corresponding outer foil pad;
first terminal means connected to said circuit board, said first terminal means including a plurality of electrically conductive pin members, each pin member electrically connected to a corresponding inner foil pad;
said first terminal means further including a plurality of electrically conductive pin accepting members, each pin member electrically connected to an associated first terminal means pin member and each pin accepting member is arranged to accept a respective and associated chip carrier connecting pin, therein, connecting said circuit board and said foil paths to said chip carrier with said semiconductor chip: and second terminal means connected to said circuit board, said second terminal means including a plurality of electrically conductive pin members, each of said second terminal means pin members connected to a corresponding outer foil pad of said circuit card, said second terminal means pin members providing for selective electrical connection of said test probe apparatus to said semiconductor chip in said leaded chip carrier.
2. A test point adaptor as claimed in claim 1, wherein there is further included third terminal means including a plurality of electrically conductive pin accepting members, each of said third terminal means pin accepting members is connected to a corre-sponding pin member of said first terminal means, and said third terminal means further including a plurality of pin members electrically connected to an associated pin accepting member, each of said pin members of said third terminal means being further connectable to printed wiring card means.
3. A test point adaptor as claimed in claim 2, said printed wiring card means is a master printed wiring card assembly used for in circuit testing of said semiconductor chip.
4. A test point adaptor as claimed in claim 3, said first terminal means comprises a plurality of terminal strip devices each of said terminal strip devices including at least one electrical socket for accepting a pin therein, and a terminal pin electrically connected to an associated socket extending from said terminal strip device.
5. A test point adaptor as claimed in claim 4, said connection of said terminal strip device terminal pins to each of said inner foil pads includes a soldered connection.
6. A test point adaptor as claimed in claim 5, said second terminal means comprises a plurality of terminal strip devices, each said terminal strip device including first and second terminal pins, and each first terminal pin electrically connected to an associated second terminal pin, and each second terminal pin connected to a corresponding outer foil pad, and each first terminal pin arranged to accept and make an electrical connection to said test probe apparatus.
7. A test point adaptor as claimed in claim 6, said connection of said terminal strip device second terminal pins to each of said outer foil pads includes a soldered connection.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US87607086A | 1986-06-19 | 1986-06-19 | |
| US876,070 | 1986-06-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1273130A true CA1273130A (en) | 1990-08-21 |
Family
ID=25366943
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000539718A Expired - Fee Related CA1273130A (en) | 1986-06-19 | 1987-06-15 | Test point adapter for chip carrier sockets |
Country Status (3)
| Country | Link |
|---|---|
| BE (1) | BE1000081A7 (en) |
| CA (1) | CA1273130A (en) |
| IT (1) | IT1204635B (en) |
-
1987
- 1987-05-18 IT IT20563/87A patent/IT1204635B/en active
- 1987-06-15 CA CA000539718A patent/CA1273130A/en not_active Expired - Fee Related
- 1987-06-17 BE BE8700660A patent/BE1000081A7/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| IT1204635B (en) | 1989-03-10 |
| BE1000081A7 (en) | 1988-02-02 |
| IT8720563A0 (en) | 1987-05-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKLA | Lapsed |