JPS58106854A - Integrated circuit - Google Patents
Integrated circuitInfo
- Publication number
- JPS58106854A JPS58106854A JP20480481A JP20480481A JPS58106854A JP S58106854 A JPS58106854 A JP S58106854A JP 20480481 A JP20480481 A JP 20480481A JP 20480481 A JP20480481 A JP 20480481A JP S58106854 A JPS58106854 A JP S58106854A
- Authority
- JP
- Japan
- Prior art keywords
- terminals
- integrated circuit
- package
- circuit
- probe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本実明線集積回路に関し、特にＤＩＰ型集積回路に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a real-line integrated circuit, and particularly to a DIP type integrated circuit.
従来、ＤＩＰ［集積回路は直方体に近いパッケージの長
手方向の側面に外部接続用の端子の列が２列並べられた
構造を有しておシ、印刷回路基板等会の実装に適する構
造になりている。Conventionally, DIP [integrated circuits] have a structure in which two rows of external connection terminals are arranged on the longitudinal side of a nearly rectangular parallelepiped package, and the structure is suitable for mounting on printed circuit boards. ing.
最近の電子装置の小型化に伴い、印刷回路基板への実装
密度が高く表ってきている。集積回路を＊鋏した印刷回
路基板の試験にはＩＣクリップ方式のインサーキット・
テスタが用いられているが、集積回路の高書度実装化に
伴い集積回路間の隙間が狭くな、９、ＩＣクリップが入
シにくくなシ被試験集積回路に接続できなくなるという
欠点があった。With the recent miniaturization of electronic devices, the mounting density on printed circuit boards has become high. For testing printed circuit boards containing integrated circuits*, we use an IC clip-type in-circuit tester.
Testers have been used, but as integrated circuits have become more highly integrated, the gaps between integrated circuits have become narrower, and the IC clips have become difficult to insert, making it impossible to connect them to the integrated circuit under test. .
本発明は上記欠点を除去し、印刷回路基板に高書度実装
してもインサーキット・テスタが支障なく使用でき、回
路試験ができる構造を有する集糠回路を提供すゐもので
ある。The present invention eliminates the above-mentioned drawbacks and provides a condenser circuit having a structure that allows the use of an in-circuit tester without any trouble even when mounted on a printed circuit board with high accuracy and allows circuit testing.
本発明の集積回路は、パッケージの側面と上面とに外部
接続用の端子を設け、前記側面の端子と土間の端子とが
１対１対応で電気的に接続されて構成される。The integrated circuit of the present invention is configured such that external connection terminals are provided on the side surface and the top surface of the package, and the terminals on the side surface and the terminals on the dirt floor are electrically connected in a one-to-one correspondence.
本発明の実施例について図画を用いて説明する。Embodiments of the present invention will be described using drawings.
第１図は本発明の一実施例の一部切欠き斜視図である。FIG. 1 is a partially cutaway perspective view of an embodiment of the present invention.
集積回路１０のパッケージの長手側の側面１１゜１１′
にそれぞれ外部引出し用の端子１３．１３’の列が設け
られている。パッケージの上面１２にも端子１４．１４
’の列が設けられる。端子１３と１４．１３′と１４′
とはそれぞれ１対１対応でパッケージ内で電気的に接続
される。Long side surface 11° 11' of package of integrated circuit 10
A row of terminals 13, 13' for external extraction is provided in each of the terminals 13, 13'. Terminals 14.14 are also located on the top surface 12 of the package.
' column is provided. Terminals 13 and 14.13' and 14'
are electrically connected within the package in a one-to-one correspondence.
第２図は館１図に示す一１！施例の試験を行うときに使
用されるインサーキット・テスタのプローブの一例の斜
視図である。Figure 2 is the one shown in Figure 1! FIG. 2 is a perspective view of an example of a probe of an in-circuit tester used when testing an example.
プ費−ブ２０はほぼ直方体のパッケージの一面にプルー
プビン２１ 、２１’の列を有し、反対面にフラット−
ケーブル２２を取付け、プａ −フヒン２１．２１’
と電気的に接続せしめる。プローブピン２１．２１’は
第１図の集積回路１０の上面の端子１４．１４’の列と
同じ位置に配列されている。The probe 20 has a row of probe bins 21, 21' on one side of a substantially rectangular parallelepiped package, and a flat column on the opposite side.
Attach cable 22 and connect cable 21.21'
to be electrically connected. The probe pins 21.21' are arranged in the same position as the rows of terminals 14.14' on the top surface of the integrated circuit 10 of FIG.
従って、プルーブビン２１．２１’を端子１４．１４’
に上から接触せしめることＫよシ集積回路１０の試験を
行うことができる。このように集積回路の上面に外部接
続用の端子を設叶ておくと、集積回路１０の側面の端子
１３，１３’とＩＣクリップとの接触をとる必要がなく
カシ、集積回路の印刷回路基板への高密度実装が可能と
なる。Therefore, probe bin 21.21' is connected to terminal 14.14'.
The integrated circuit 10 can be tested by contacting it from above. By providing terminals for external connections on the top surface of the integrated circuit in this way, there is no need to make contact between the terminals 13 and 13' on the side of the integrated circuit 10 and the IC clip. High-density packaging becomes possible.
以上詳細に説明したように、本発明によれば、印刷回路
基板に高密度実装してもインサーキット−テスタによる
回路試験が容易にできる集積回路が得られるのでその効
果は大きい。As described above in detail, the present invention has great effects because it can provide an integrated circuit that can be easily tested using an in-circuit tester even when it is mounted on a printed circuit board at high density.
第１図は本発明の一実施例の一部切欠き斜視図、第２図
紘第１図に示す一実施例の試験を行うときに使用される
インサーキット会テスタのプローブの一例の斜視図であ
る。
１０・・・・・・集積回路、１１．１１’・・・・・・
側面、１２・・・・・・上面、１３．１３’・・・・・
・端子、１４．１４’・・・・・・端子、２０・・・・
・・プルーブ、２１，２１’・・・・・・プローブビン
、２２・・・・・・フラット・ケーブル。
′°隼Ｉ凹
ゴ′
ト
隼２ｇ
）−
２２FIG. 1 is a partially cutaway perspective view of an embodiment of the present invention, and FIG. 2 is a perspective view of an example of a probe of an in-circuit tester used when testing the embodiment shown in FIG. 1. It is. 10... integrated circuit, 11.11'...
Side, 12...Top, 13.13'...
・Terminal, 14.14'...Terminal, 20...
...Probe, 21, 21'...Probe bin, 22...Flat cable. '°Hayabusa I concave go' To Hayabusa 2g )-22
Claims (1)
前記側面の端子と上面の端子とが１対１対応で電気的に
接続されている仁とを特徴とする集積回路。Terminals for external connections are provided on the side and top of the package.
An integrated circuit characterized in that the terminals on the side surface and the terminals on the top surface are electrically connected in a one-to-one correspondence.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20480481A JPS58106854A (en) | 1981-12-18 | 1981-12-18 | Integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20480481A JPS58106854A (en) | 1981-12-18 | 1981-12-18 | Integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58106854A true JPS58106854A (en) | 1983-06-25 |
| JPS6347273B2 JPS6347273B2 (en) | 1988-09-21 |
Family
ID=16496634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20480481A Granted JPS58106854A (en) | 1981-12-18 | 1981-12-18 | Integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58106854A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58106950U (en) * | 1982-01-13 | 1983-07-21 | 富士通株式会社 | Semiconductor device package |
| JPS6034047A (en) * | 1983-08-05 | 1985-02-21 | Nec Corp | Integrated circuit package |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5025466U (en) * | 1973-06-30 | 1975-03-24 | ||
| JPS5476675U (en) * | 1977-11-10 | 1979-05-31 | ||
| JPS55115061U (en) * | 1979-02-05 | 1980-08-13 | ||
| JPS5688343A (en) * | 1979-12-21 | 1981-07-17 | Fujitsu Ltd | Multichip type semiconductor package |
| JPS5784755U (en) * | 1980-11-14 | 1982-05-25 |
-
1981
- 1981-12-18 JP JP20480481A patent/JPS58106854A/en active Granted
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5025466U (en) * | 1973-06-30 | 1975-03-24 | ||
| JPS5476675U (en) * | 1977-11-10 | 1979-05-31 | ||
| JPS55115061U (en) * | 1979-02-05 | 1980-08-13 | ||
| JPS5688343A (en) * | 1979-12-21 | 1981-07-17 | Fujitsu Ltd | Multichip type semiconductor package |
| JPS5784755U (en) * | 1980-11-14 | 1982-05-25 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58106950U (en) * | 1982-01-13 | 1983-07-21 | 富士通株式会社 | Semiconductor device package |
| JPS6034047A (en) * | 1983-08-05 | 1985-02-21 | Nec Corp | Integrated circuit package |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6347273B2 (en) | 1988-09-21 |
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