JPH04369253A - Semiconductor integrated circuit package - Google Patents

Semiconductor integrated circuit package

Info

Publication number
JPH04369253A
JPH04369253A JP3145053A JP14505391A JPH04369253A JP H04369253 A JPH04369253 A JP H04369253A JP 3145053 A JP3145053 A JP 3145053A JP 14505391 A JP14505391 A JP 14505391A JP H04369253 A JPH04369253 A JP H04369253A
Authority
JP
Japan
Prior art keywords
package
pad
terminal
conductor
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3145053A
Other languages
Japanese (ja)
Inventor
Hitoshi Ishizuki
石附　仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3145053A priority Critical patent/JPH04369253A/en
Publication of JPH04369253A publication Critical patent/JPH04369253A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias

Abstract

PURPOSE:To observe the electric operation of an IC chip with a surface conductor by branching a conductor pattern which electrically connects the terminal of an IC chip with the external terminal of an IC package electrically, and connecting the elements with the conductor plate arranged in island shape on the surface of the package. CONSTITUTION:The pad 7 of an IC pad 4 is connected to a package internal pad by a conductive wire 5 for chip-package connection, and the package internal pad 8 is electrically connected with a package external pad 3 via a package internal conductor pattern 2. Furthermore, the package internal conductor pattern 2 is connected to the surface conductor pad 1. Hereby, even with a multipin package with a short terminal width, it becomes possible to perform measurement easily at the time of observation of electric operation by bringing the terminal of the IC package into contact with the conductor plate at the surface of the package with a large contact area.

Description

【発明の詳細な説明】[Detailed description of the invention]

【０００１】0001

【産業上の利用分野】本発明は半導体集積回路パッケー
ジ、特に、多ピンかつリードピッチ間小の高密度実装用
の半導体集積回路パッケージに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit package, and particularly to a semiconductor integrated circuit package for high-density packaging with a large number of pins and a small lead pitch.

【０００２】0002

【従来の技術】従来、この種の表面実装用の集積回路パ
ッケージ（以下ＩＣパッケージと呼ぶ）はＩＣパッケー
ジ内部を通る導体パターンを介してＩＣの端子とＩＣパ
ッケージの外部端子は電気的に接続されており、その接
続はいっさい外部からは見えない構造となっている。そ
の為ＩＣチップの動作を観測しようとする場合は、パッ
ケージ外部端子に測定機器の測定端子を接触させる方法
で観測を行っていた。[Prior Art] Conventionally, in this type of surface-mount integrated circuit package (hereinafter referred to as an IC package), terminals of the IC and external terminals of the IC package are electrically connected via a conductive pattern passing inside the IC package. The structure is such that all connections are invisible from the outside. Therefore, when attempting to observe the operation of an IC chip, the observation has been carried out by bringing a measuring terminal of a measuring device into contact with an external terminal of the package.

【０００３】0003

【発明が解決しようとする課題】上述した従来のＩＣパ
ッケージを使用した場合、ＩＣの端子はパッケージ内部
に構成されている導体パターンを介してＩＣパッケージ
の外部端子と接続されているため、信号端子の電気的動
作の観測を行う際は、ＩＣパッケージの外部端子に測定
機器の測定端子、たとえばプローブ等を接触させて行う
ことになるが、信号ピンの多ピン化かつパッケージの小
型化を実現したＩＣパッケージになると、パッケージ外
部端子巾および端子間長が短くなってしまうため、測定
端子を被測定端子に接触させる際に、隣りの端子に接触
するなど目的の端子のみとの接触が困難であった。[Problems to be Solved by the Invention] When using the above-mentioned conventional IC package, the terminals of the IC are connected to the external terminals of the IC package through the conductor pattern configured inside the package, so the signal terminal When observing the electrical operation of an IC package, it is necessary to contact the measurement terminal of a measuring device, such as a probe, with the external terminal of the IC package. When using an IC package, the external package terminal width and the length between the terminals are shortened, so when contacting the measurement terminal with the terminal under test, it is difficult to contact only the desired terminal, such as contacting an adjacent terminal. Ta.

【０００４】また不良解析の対象となるＩＣパッケージ
は１度プリント基板に実装されたものを取りはずすこと
を前提としているため、時として外部端子の欠損が起こ
る。その時には、電気的動作の観測は測定端子を接触さ
せることが不可能となる欠点もあった。[0004]Furthermore, since it is assumed that the IC package to be subjected to failure analysis is once mounted on a printed circuit board and then removed, external terminals may sometimes be missing. At that time, there was also the drawback that it was impossible to make contact with the measurement terminals to observe electrical behavior.

【０００５】[0005]

【課題を解決するための手段】本発明の半導体集積回路
パッケージはＩＣチップの端子とＩＣパッケージの外部
端子を電気的に接続する導体パターンを分岐させ、ＩＣ
パッケージの表面に島状に配置された導体板と接続され
ている。[Means for Solving the Problems] The semiconductor integrated circuit package of the present invention has a conductor pattern that electrically connects the terminals of the IC chip and the external terminals of the IC package with branches.
It is connected to a conductor plate arranged like an island on the surface of the package.

【０００６】[0006]

【実施例】次に、本発明について図面を参照して説明す
る。図１（ａ）は本発明の一実施例の平面図、図１（ｂ
）は図１（ａ）のＡ−Ａ線断面図、図１（ｃ）は図１（
ａ）のＢ−Ｂ線断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1(a) is a plan view of an embodiment of the present invention, and FIG. 1(b) is a plan view of an embodiment of the present invention.
) is a sectional view taken along line A-A in Figure 1(a), and Figure 1(c) is a cross-sectional view taken along line A-A in Figure 1(a).
It is a BB sectional view of a).

【０００７】ＩＣチップ４のパッド７は、チップ−パッ
ケージ接続用導線５によりパッケージ内部パッド８と接
続されており、パッケージ内部パッド８はパッケージ内
部導体パターン２を経由してパッケージ外部端子３と電
気的接続がなされている。さらにパッケージ内部導体パ
ターン２は表面導体パッド１と図１（ａ），（ｂ）の様
に接続されている。The pad 7 of the IC chip 4 is connected to the package internal pad 8 by a chip-package connecting conductor 5, and the package internal pad 8 is electrically connected to the package external terminal 3 via the package internal conductor pattern 2. A connection has been made. Furthermore, the package internal conductor pattern 2 is connected to the surface conductor pad 1 as shown in FIGS. 1(a) and 1(b).

【０００８】[0008]

【発明の効果】以上説明したように本発明は、ＩＣパッ
ケージ表面に導体でできたパッドを設置し、かつその導
体パッドをＩＣチップの端子とパッケージ外部の端子と
を電気的に接続している内部導体パターンと接続するこ
とにより、パッケージ端子間ピッチが短く、端子巾の短
い高密度表面実装タイプの多ピンＩＣパッケージでも、
電気的動作の観測の時は、接触困難なＩＣパッケージの
端子に測定機器の測定端子を接触させなくても、接触面
積の大きいパッケージ表面の導体板に接触させることに
より、容易に測定を行うことが可能となる。また、パッ
ケージ外部端子の欠損があった場合でも同様に容易に測
定が可能となる効果がある。[Effects of the Invention] As explained above, in the present invention, a pad made of a conductor is installed on the surface of an IC package, and the conductor pad is electrically connected between the terminal of the IC chip and the terminal outside the package. By connecting with the internal conductor pattern, even high-density surface mount type multi-pin IC packages with short pitch between package terminals and short terminal width,
When observing electrical behavior, measurements can be easily made by touching the conductor plate on the surface of the package, which has a large contact area, without having to bring the measuring terminal of the measuring device into contact with the difficult-to-reach terminal of the IC package. becomes possible. Further, even if there is a defect in the external terminal of the package, measurement can be easily performed.

【図面の簡単な説明】[Brief explanation of drawings]

【図１】（ａ）〜（ｃ）は本発明の一実施例を示す平面
図および断面図である。FIGS. 1(a) to 1(c) are a plan view and a sectional view showing an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１　　　　表面導体パッド ２　　　　内部導体パターン ３　　　　パッケージ外部リード線 ４　　　　ＩＣチップ ５　　　　チップ−パッケージ接続用導線６　　　　半
導体集積回路パッケージ ７　　　　ＩＣパッド ８　　　　パッケージ内部パッド1 Surface conductor pad 2 Internal conductor pattern 3 Package external lead wire 4 IC chip 5 Chip-package connection conductor 6 Semiconductor integrated circuit package 7 IC pad 8 Package internal pad

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】　　ＩＣチップの端子と高密度表面実装タ
イプのパッケージ外部端子との電気的接続を行なってい
る内部導体パターンを分岐させ、パッケージ表面に島状
に配置された導体板と接続することにより、ＩＣチップ
の電気的動作の観測を前記表面導体板で行うことが可能
となる半導体集積回路パッケージ。[Claim 1] The internal conductor pattern that electrically connects the terminals of the IC chip and the external terminals of a high-density surface mount type package is branched and connected to a conductor plate arranged in an island shape on the surface of the package. A semiconductor integrated circuit package in which the electrical operation of an IC chip can be observed using the surface conductor plate.
JP3145053A 1991-06-18 1991-06-18 Semiconductor integrated circuit package Pending JPH04369253A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3145053A JPH04369253A (en) 1991-06-18 1991-06-18 Semiconductor integrated circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3145053A JPH04369253A (en) 1991-06-18 1991-06-18 Semiconductor integrated circuit package

Publications (1)

Publication Number Publication Date
JPH04369253A true JPH04369253A (en) 1992-12-22

Family

ID=15376295

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3145053A Pending JPH04369253A (en) 1991-06-18 1991-06-18 Semiconductor integrated circuit package

Country Status (1)

Country Link
JP (1) JPH04369253A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5670825A (en) * 1995-09-29 1997-09-23 Intel Corporation Integrated circuit package with internally readable permanent identification of device characteristics
US5686759A (en) * 1995-09-29 1997-11-11 Intel Corporation Integrated circuit package with permanent identification of device characteristics and method for adding the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5670825A (en) * 1995-09-29 1997-09-23 Intel Corporation Integrated circuit package with internally readable permanent identification of device characteristics
US5686759A (en) * 1995-09-29 1997-11-11 Intel Corporation Integrated circuit package with permanent identification of device characteristics and method for adding the same

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