JPS5645078A - Manufacturing of semiconductor device - Google Patents
Manufacturing of semiconductor deviceInfo
- Publication number
- JPS5645078A JPS5645078A JP12151279A JP12151279A JPS5645078A JP S5645078 A JPS5645078 A JP S5645078A JP 12151279 A JP12151279 A JP 12151279A JP 12151279 A JP12151279 A JP 12151279A JP S5645078 A JPS5645078 A JP S5645078A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- resistance value
- wiring
- gate
- polycrystalline
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000012535 impurity Substances 0.000 abstract 2
- 239000012528 membrane Substances 0.000 abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract 1
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 239000006185 dispersion Substances 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 229910052698 phosphorus Inorganic materials 0.000 abstract 1
- 239000011574 phosphorus Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Non-Volatile Memory (AREA)
Abstract
PURPOSE:To facilitate control of resistance value, when providing a semiconductor device with an electrode or a wiring having a desired resistance value, by patterning with a polycrystalline Si layer and also by giving a resistance value by dispersion of impurity from a PSG layer provided on the Si layer. CONSTITUTION:A gate SiO2 membrane 2 is attached onto a P type Si substrate 1, a polycrystalline Si layer 3 which is used for wiring of a gate electrode is piled on the gate SiO2 membrane 2 by CVD method, and a PSG layer 4 which is to become an impurity layer is attached onto surface of the layer 3. And then, in order to enable a part of the Si layer 3 to remain as a wiring for a gate electrode, unnecessary portion of the Si layer 3 is removed at first by etching, the layer 3 is self- adjusted using the remaining layer 4 as a mask so as to obtain a layer 3', and by heat-treating thus obtained layer 3', phosphorus content in the layer 4' is dispersed to obtain a desired resistance value for the layer 3'. And then, unnecessary layer 4' is removed, and an N type source region 51 and a drain region 52 are dispersedly formed in the substrate 1 on the sides of the layer 3' using the layer 3' as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12151279A JPS5645078A (en) | 1979-09-20 | 1979-09-20 | Manufacturing of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12151279A JPS5645078A (en) | 1979-09-20 | 1979-09-20 | Manufacturing of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5645078A true JPS5645078A (en) | 1981-04-24 |
Family
ID=14813028
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12151279A Pending JPS5645078A (en) | 1979-09-20 | 1979-09-20 | Manufacturing of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5645078A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5712177A (en) * | 1994-08-01 | 1998-01-27 | Motorola, Inc. | Method for forming a reverse dielectric stack |
-
1979
- 1979-09-20 JP JP12151279A patent/JPS5645078A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5712177A (en) * | 1994-08-01 | 1998-01-27 | Motorola, Inc. | Method for forming a reverse dielectric stack |
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