JPS5645068A - Manufacture of semiconductor - Google Patents

Manufacture of semiconductor

Info

Publication number
JPS5645068A
JPS5645068A JP12062979A JP12062979A JPS5645068A JP S5645068 A JPS5645068 A JP S5645068A JP 12062979 A JP12062979 A JP 12062979A JP 12062979 A JP12062979 A JP 12062979A JP S5645068 A JPS5645068 A JP S5645068A
Authority
JP
Japan
Prior art keywords
films
wires
sio2
electrodes
thick
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12062979A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6341224B2 (enrdf_load_stackoverflow
Inventor
Yasunobu Osa
Jun Sugiura
Kazuhiro Komori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12062979A priority Critical patent/JPS5645068A/ja
Publication of JPS5645068A publication Critical patent/JPS5645068A/ja
Publication of JPS6341224B2 publication Critical patent/JPS6341224B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP12062979A 1979-09-21 1979-09-21 Manufacture of semiconductor Granted JPS5645068A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12062979A JPS5645068A (en) 1979-09-21 1979-09-21 Manufacture of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12062979A JPS5645068A (en) 1979-09-21 1979-09-21 Manufacture of semiconductor

Publications (2)

Publication Number Publication Date
JPS5645068A true JPS5645068A (en) 1981-04-24
JPS6341224B2 JPS6341224B2 (enrdf_load_stackoverflow) 1988-08-16

Family

ID=14790946

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12062979A Granted JPS5645068A (en) 1979-09-21 1979-09-21 Manufacture of semiconductor

Country Status (1)

Country Link
JP (1) JPS5645068A (enrdf_load_stackoverflow)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57501099A (enrdf_load_stackoverflow) * 1980-06-19 1982-06-24
US5019527A (en) * 1989-08-11 1991-05-28 Kabushiki Kaisha Toshiba Method of manufacturing non-volatile semiconductor memories, in which selective removal of field oxidation film for forming source region and self-adjusted treatment for forming contact portion are simultaneously performed
US5235200A (en) * 1990-01-29 1993-08-10 Hitachi, Ltd. Semiconductor integrated circuit device
US5817556A (en) * 1994-09-30 1998-10-06 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor memory device including memory cells having connected source regions

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57501099A (enrdf_load_stackoverflow) * 1980-06-19 1982-06-24
US5019527A (en) * 1989-08-11 1991-05-28 Kabushiki Kaisha Toshiba Method of manufacturing non-volatile semiconductor memories, in which selective removal of field oxidation film for forming source region and self-adjusted treatment for forming contact portion are simultaneously performed
US5235200A (en) * 1990-01-29 1993-08-10 Hitachi, Ltd. Semiconductor integrated circuit device
US5427966A (en) * 1990-01-29 1995-06-27 Hitachi, Ltd. Process for fabricating a semiconductor device having floating gate and control gate electrodes
US5817556A (en) * 1994-09-30 1998-10-06 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor memory device including memory cells having connected source regions

Also Published As

Publication number Publication date
JPS6341224B2 (enrdf_load_stackoverflow) 1988-08-16

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