JPS5638823A - Formation of polyimide pattern - Google Patents

Formation of polyimide pattern

Info

Publication number
JPS5638823A
JPS5638823A JP9942979A JP9942979A JPS5638823A JP S5638823 A JPS5638823 A JP S5638823A JP 9942979 A JP9942979 A JP 9942979A JP 9942979 A JP9942979 A JP 9942979A JP S5638823 A JPS5638823 A JP S5638823A
Authority
JP
Japan
Prior art keywords
polyimide
polyimide precursor
pattern
etching
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9942979A
Other languages
Japanese (ja)
Inventor
Yoshi Hiramoto
Masuichi Eguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toray Industries Inc
Original Assignee
Toray Industries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toray Industries Inc filed Critical Toray Industries Inc
Priority to JP9942979A priority Critical patent/JPS5638823A/en
Publication of JPS5638823A publication Critical patent/JPS5638823A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To obtain the polyimide pattern providing with a hole having a desired shape of sectional area by a method wherein a pattern of two layer structure consisting of a nonphotosensitive polyimide precursor or a polyimide [A] and a photosensitive polyimide precursor is formed on a substrate. CONSTITUTION:A solution of nonphotosensitive polyimide precursor and a solution of photosensitive polyimide precursor are applied in order on a semiconductor substrate 3, and is dried at 80 deg.C for 30min to form coats 2, 1. Using a prescribed mask, the photosensitive polyimide precursor film 1 is exposed and is developed to form a pattern. The whole is heat treated to convert the both polyimide precursors to polyimides, and the layer 2 is etched using a polyimide etching liquid. By this way, selecting the etching time and the thickness of each film, a polyimide pattern providing with a hole having a desired sectional area can be obtained. For example, by the etching for 5min, a conical hole as shown in the figure can be obtained, and by the etching for 20min, a side etched type hole can be obtained.
JP9942979A 1979-08-06 1979-08-06 Formation of polyimide pattern Pending JPS5638823A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9942979A JPS5638823A (en) 1979-08-06 1979-08-06 Formation of polyimide pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9942979A JPS5638823A (en) 1979-08-06 1979-08-06 Formation of polyimide pattern

Publications (1)

Publication Number Publication Date
JPS5638823A true JPS5638823A (en) 1981-04-14

Family

ID=14247197

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9942979A Pending JPS5638823A (en) 1979-08-06 1979-08-06 Formation of polyimide pattern

Country Status (1)

Country Link
JP (1) JPS5638823A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03133132A (en) * 1989-10-06 1991-06-06 Internatl Business Mach Corp <Ibm> Conductor pattern formation
CN103065961A (en) * 2011-10-21 2013-04-24 上海华虹Nec电子有限公司 Polyimide passivation layer manufacture processing method applied to high voltage devices

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4965783A (en) * 1972-10-25 1974-06-26
JPS49122979A (en) * 1973-03-27 1974-11-25

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4965783A (en) * 1972-10-25 1974-06-26
JPS49122979A (en) * 1973-03-27 1974-11-25

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03133132A (en) * 1989-10-06 1991-06-06 Internatl Business Mach Corp <Ibm> Conductor pattern formation
CN103065961A (en) * 2011-10-21 2013-04-24 上海华虹Nec电子有限公司 Polyimide passivation layer manufacture processing method applied to high voltage devices

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