JPH0425047A - Preparation of semiconductor device - Google Patents
Preparation of semiconductor deviceInfo
- Publication number
- JPH0425047A JPH0425047A JP12579090A JP12579090A JPH0425047A JP H0425047 A JPH0425047 A JP H0425047A JP 12579090 A JP12579090 A JP 12579090A JP 12579090 A JP12579090 A JP 12579090A JP H0425047 A JPH0425047 A JP H0425047A
- Authority
- JP
- Japan
- Prior art keywords
- protective film
- electrode
- polyimide resin
- film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 230000001681 protective effect Effects 0.000 claims abstract description 24
- 229920001721 polyimide Polymers 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000009719 polyimide resin Substances 0.000 claims abstract description 12
- 238000001259 photo etching Methods 0.000 claims abstract description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000005553 drilling Methods 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000000059 patterning Methods 0.000 abstract description 3
- 239000004642 Polyimide Substances 0.000 abstract description 2
- 238000001312 dry etching Methods 0.000 abstract description 2
- 238000005530 etching Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置の製造方法のうち保護又形成後
の電極部穴明は方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for protecting or drilling an electrode portion after formation, among methods of manufacturing a semiconductor device.
この発明は２層構造の保護膜を有する半導体装置の感光
性ポリイミド樹脂からなる」二層部保護膜に電極用の穴
を形成し、ポリイミド樹脂をマスクとして下層部保護膜
も電極用の穴の延長としてエツチング除去するというも
のである。This invention consists of a photosensitive polyimide resin for a semiconductor device having a two-layer protective film.The two-layer protective film is made of a photosensitive polyimide resin, and the lower protective film is also used to form electrode holes using the polyimide resin as a mask. As an extension, it is removed by etching.
従来、第２図（ａ）に示すように下層保護膜１を堆積後
、１回目のフォト及び工・ノチングにより第２図ｆｂｌ
に示すように、下層保護膜１の電極部穴明けを行い、さ
らに第２図（ｃ）のように上層保護膜６の１■積を行っ
た後に、第２図（ｄ）のように２回目のフォト及びエツ
チングにより」二層保護膜６の電極部穴明りを行ってい
た。Conventionally, after depositing the lower protective film 1 as shown in FIG.
As shown in FIG. 2, holes are made in the electrode portion of the lower protective film 1, and after the upper protective film 6 is deposited by 1 inch as shown in FIG. 2(c), two holes are formed as shown in FIG. 2(d). By the second photo-etching and etching process, holes in the electrode portion of the two-layer protective film 6 were made.
しかし、従来方法では２Ｎ保護膜の電極部を穴明けする
ために２回のフォ１〜及びエツチングによるバターニン
グを行う必要があった。そこでこの発明は１回のフォ１
−及びエツチングのバターニングにより２Ｎ保護膜電極
部の穴明けを行うことを目的としている。However, in the conventional method, in order to form a hole in the electrode portion of the 2N protective film, it was necessary to carry out patterning by two processes of photolithography and etching. Therefore, this invention
- The purpose is to make holes in the 2N protective film electrode portion by patterning and etching.
上記問題点を解決するために、この発明は上層保護膜及
び電極部穴明は形成に感光性ポリイミド樹脂を用いた工
程を行い、さらにそのポリイミド樹脂をマスクと、して
下層保護膜電極部の穴明りをエツチングにより行うよう
にしている。In order to solve the above problems, the present invention performs a process using photosensitive polyimide resin to form the upper protective film and electrode part holes, and further uses the polyimide resin as a mask to form the lower protective film electrode part. The holes are made by etching.
」二記のように感光性ポリイミド樹脂を用いた工程を行
うことにより従来２回行っていたフメト及びエツチング
を１回にすることができる。By carrying out the process using a photosensitive polyimide resin as described in Section 2 above, it is possible to reduce the number of times of etching and etching, which were conventionally performed twice, to one time.
以下にこの発明の実施例を図面に基づいて説明する。 Embodiments of the present invention will be described below based on the drawings.
第１図（・））〜（Ｃ）は、半導体装置の２層保護膜と
電極部穴明けを形成する工程順断面図である。第１図ｔ
ａ＋は半導体基板３に金属配線２したものに下層保護膜
１としてＰＳＧ膜を堆積した断面図である。FIGS. 1(-) to 1(C) are cross-sectional views in the order of steps for forming a two-layer protective film and electrode portion holes of a semiconductor device. Figure 1
a+ is a cross-sectional view of a semiconductor substrate 3 with metal wiring 2 on which a PSG film is deposited as a lower protective film 1;
第１図（ｂ）は、上記の半導体装置に感光性ポリイミド
樹脂４を塗布した後、電極部以外を露光し、現像乙こよ
り未露光部の電極部を除去し、穴明げを行っている。第
１図（Ｃ１は感光性ポリイミド４を熱処理で硬化させた
後、それをマスクとして下層保護膜１ （ＰＳＧ膜）
をドライエッチにより除去し電極部穴明けを行った半導
体装置の断面である。Figure 1(b) shows that after coating the above semiconductor device with photosensitive polyimide resin 4, parts other than the electrode parts are exposed to light, the unexposed part of the electrode part is removed after development, and holes are made. . Figure 1 (C1 is lower protective film 1 (PSG film) after curing photosensitive polyimide 4 by heat treatment and using it as a mask.
This is a cross-section of a semiconductor device in which electrode portions were removed by dry etching and holes were made for electrode portions.
本発明は、以上説明したように２層保護服を有する半導
体装置で、上層の保護膜を感光性ポリイミド樹脂を用い
た工程を使用するごとによりフォ１−及びエソチング工
程を１回づつなくすことができるという効果がある。As explained above, the present invention is a semiconductor device having a two-layer protective film, and by using a process using a photosensitive polyimide resin for the upper protective film, it is possible to eliminate one photolithography and ethoching process. There is an effect that it can be done.
第１図（ａ）〜（Ｃ）は本発明にかかる２層保護膜電極
部の穴明りをするだめの製造工程順断面図、第２図（ａ
ｌ〜（ｄ＋は従来の２層保護膜電極部の穴明けをするだ
めの製造工程順断面図である。
１・・・ＰＳＧ膜
２・・・金属配線電極部
３・・・半導体基板
４・・・感光性ポリイミド樹脂
５・・・レジスト
６・・・窒化珪素膜
以」ニ
出願人 セイコー電子工業株式会社
代理人 弁理士 林 敬 之 助FIGS. 1(a) to (C) are cross-sectional views in the order of manufacturing steps of a receptacle for drilling holes in a two-layer protective film electrode portion according to the present invention, and FIG. 2(a)
l~(d+ is a sectional view in the order of the manufacturing process for making a hole in a conventional two-layer protective film electrode part. 1...PSG film 2...Metal wiring electrode part 3...Semiconductor substrate 4... ...Photosensitive polyimide resin 5...Resist 6...Silicon nitride film" Applicant: Seiko Electronic Industries Co., Ltd. Patent attorney: Keinosuke Hayashi
Claims (1)
、上層保護膜であるポリイミド樹脂に電極部穴明けを形
成するためのフォト・エッチ工程を有することを特徴と
する半導体装置の製造方法。A method for manufacturing a semiconductor device having a two-layer protective film, the method comprising a photo-etching process for forming holes in an electrode portion in a polyimide resin serving as an upper protective film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12579090A JPH0425047A (en) | 1990-05-16 | 1990-05-16 | Preparation of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12579090A JPH0425047A (en) | 1990-05-16 | 1990-05-16 | Preparation of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0425047A true JPH0425047A (en) | 1992-01-28 |
Family
ID=14918933
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12579090A Pending JPH0425047A (en) | 1990-05-16 | 1990-05-16 | Preparation of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0425047A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6127099A (en) * | 1995-04-24 | 2000-10-03 | Nec Corporation | Method of producing a semiconductor device |
| KR100437621B1 (en) * | 1996-10-30 | 2004-08-25 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
-
1990
- 1990-05-16 JP JP12579090A patent/JPH0425047A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6127099A (en) * | 1995-04-24 | 2000-10-03 | Nec Corporation | Method of producing a semiconductor device |
| KR100437621B1 (en) * | 1996-10-30 | 2004-08-25 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
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