JPS5629719A - Constant voltage circuit - Google Patents

Constant voltage circuit

Info

Publication number
JPS5629719A
JPS5629719A JP10424479A JP10424479A JPS5629719A JP S5629719 A JPS5629719 A JP S5629719A JP 10424479 A JP10424479 A JP 10424479A JP 10424479 A JP10424479 A JP 10424479A JP S5629719 A JPS5629719 A JP S5629719A
Authority
JP
Japan
Prior art keywords
plus
source
electrode
drain regions
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10424479A
Other languages
Japanese (ja)
Inventor
Hiroshi Morito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10424479A priority Critical patent/JPS5629719A/en
Publication of JPS5629719A publication Critical patent/JPS5629719A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To obtain the desired constant voltage without increasing the area of the element, by providing two units of the depletion-type FET having the source and drain regions plus the 1st and 2nd gates each.
CONSTITUTION: For the P channel depletion type insulated gate field effect transistor FET 2 and 3, the P type source and drain regions plus the P type channel region connecting to said source and drain regions are formed within the N type semiconductor substrate, the 1st gate electrode G1 is provided on the gate insulating film on the channel region, and the source and drain electrodes S and D plus the 2nd gate electrode G2 are extracted out of the source and drain regions plus the substrate respectively. Then electrodes G1, S and G2 of the FET2 plus electrode G2 of the FET3 are connected to the plus terminal (earthed) of the power source VD2 each, along with connection of electrode D of the FET2 plus electrodes S and G1 of the FET3 each. And electrode D of the FET3 is connected to the minus terminal of the VD2.
COPYRIGHT: (C)1981,JPO&Japio
JP10424479A 1979-08-15 1979-08-15 Constant voltage circuit Pending JPS5629719A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10424479A JPS5629719A (en) 1979-08-15 1979-08-15 Constant voltage circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10424479A JPS5629719A (en) 1979-08-15 1979-08-15 Constant voltage circuit

Publications (1)

Publication Number Publication Date
JPS5629719A true JPS5629719A (en) 1981-03-25

Family

ID=14375529

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10424479A Pending JPS5629719A (en) 1979-08-15 1979-08-15 Constant voltage circuit

Country Status (1)

Country Link
JP (1) JPS5629719A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53132750A (en) * 1977-04-22 1978-11-18 Matsushita Electric Ind Co Ltd Constant voltage circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53132750A (en) * 1977-04-22 1978-11-18 Matsushita Electric Ind Co Ltd Constant voltage circuit

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