JPS56167355A - Large-scale integrated circuit package - Google Patents

Large-scale integrated circuit package

Info

Publication number
JPS56167355A
JPS56167355A JP7027280A JP7027280A JPS56167355A JP S56167355 A JPS56167355 A JP S56167355A JP 7027280 A JP7027280 A JP 7027280A JP 7027280 A JP7027280 A JP 7027280A JP S56167355 A JPS56167355 A JP S56167355A
Authority
JP
Japan
Prior art keywords
wiring
chip
substrate
pad
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7027280A
Other languages
Japanese (ja)
Inventor
Tatsuo Inoue
Hikari Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7027280A priority Critical patent/JPS56167355A/en
Publication of JPS56167355A publication Critical patent/JPS56167355A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PURPOSE:To improve the heat radiation effect of a chip as well as to accomplish the high density of a wiring by a method wherein a chip is equipped with a substrate, and the pad on the substrate and the bump on the chip are connected using a high molecular thin film on which a plurality of wiring pattern are provided. CONSTITUTION:The LSI chip 34, having a bump 36 to be used for exterior connection, is installed on the metal pad 31 of the wiring substrate 30 whereon a heat sink 38 was provided. The pad 44, to be used for connection, provided at the wiring layer end section on the organic high molecular thin film 42 having a plurality of wiring pattern layers 46 and 48, is connected to a pad 32 and a bump 36 by performing a soldering, for example. By utilizing the connecting lead having a wiring layers as above-mentioned, a high density wiring substrate 30 can be obtained. Also, a heat radiating property can be improved by directly installing a chip 34 on the substrate.
JP7027280A 1980-05-27 1980-05-27 Large-scale integrated circuit package Pending JPS56167355A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7027280A JPS56167355A (en) 1980-05-27 1980-05-27 Large-scale integrated circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7027280A JPS56167355A (en) 1980-05-27 1980-05-27 Large-scale integrated circuit package

Publications (1)

Publication Number Publication Date
JPS56167355A true JPS56167355A (en) 1981-12-23

Family

ID=13426713

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7027280A Pending JPS56167355A (en) 1980-05-27 1980-05-27 Large-scale integrated circuit package

Country Status (1)

Country Link
JP (1) JPS56167355A (en)

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