JPS56166528A - Control system for input and output device - Google Patents

Control system for input and output device

Info

Publication number
JPS56166528A
JPS56166528A JP6961880A JP6961880A JPS56166528A JP S56166528 A JPS56166528 A JP S56166528A JP 6961880 A JP6961880 A JP 6961880A JP 6961880 A JP6961880 A JP 6961880A JP S56166528 A JPS56166528 A JP S56166528A
Authority
JP
Japan
Prior art keywords
input
processing
device number
output
cpu2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6961880A
Other languages
Japanese (ja)
Other versions
JPS5936286B2 (en
Inventor
Masaru Wakamatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyo Electric Manufacturing Ltd
Original Assignee
Toyo Electric Manufacturing Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyo Electric Manufacturing Ltd filed Critical Toyo Electric Manufacturing Ltd
Priority to JP55069618A priority Critical patent/JPS5936286B2/en
Publication of JPS56166528A publication Critical patent/JPS56166528A/en
Publication of JPS5936286B2 publication Critical patent/JPS5936286B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To take a device number of high priority as an interruption address and to make the processing with priority for the processing routine of the device, by comparing a device number under present processing by an input and output control CPU with that of the other device number required for new processing. CONSTITUTION:A master CPU1 transmits a device number and a task number of input and output to a slave CPU2 for input and output control via multibus 6. The CPU2 receives it and gives and receives signlas to and from input and output devices 3-5 via an input and output bus 7. The CPU2 is provided with a circuit which makes comparison with a device number processed at present when an input and output processing request is made from other processors and produces interruption automatically if the device is one of high priority, and the device number is taken as an interruption jumped address. Thus, processing with priority is made through jumped processing routine specific to the device programed in advance. Thus, a programer of the CPU1 can make programing unified to the CPU2 without being aware of the status of the device.
JP55069618A 1980-05-27 1980-05-27 I/O device control method Expired JPS5936286B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55069618A JPS5936286B2 (en) 1980-05-27 1980-05-27 I/O device control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55069618A JPS5936286B2 (en) 1980-05-27 1980-05-27 I/O device control method

Publications (2)

Publication Number Publication Date
JPS56166528A true JPS56166528A (en) 1981-12-21
JPS5936286B2 JPS5936286B2 (en) 1984-09-03

Family

ID=13408027

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55069618A Expired JPS5936286B2 (en) 1980-05-27 1980-05-27 I/O device control method

Country Status (1)

Country Link
JP (1) JPS5936286B2 (en)

Also Published As

Publication number Publication date
JPS5936286B2 (en) 1984-09-03

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