JPS5518729A - Parallel triple system constituting method of computer system - Google Patents

Parallel triple system constituting method of computer system

Info

Publication number
JPS5518729A
JPS5518729A JP9041078A JP9041078A JPS5518729A JP S5518729 A JPS5518729 A JP S5518729A JP 9041078 A JP9041078 A JP 9041078A JP 9041078 A JP9041078 A JP 9041078A JP S5518729 A JPS5518729 A JP S5518729A
Authority
JP
Japan
Prior art keywords
case
data
interface
dissidence
decision
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9041078A
Other languages
Japanese (ja)
Other versions
JPS5931738B2 (en
Inventor
Masahiro Ueno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP53090410A priority Critical patent/JPS5931738B2/en
Publication of JPS5518729A publication Critical patent/JPS5518729A/en
Publication of JPS5931738B2 publication Critical patent/JPS5931738B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To obtain an effective parallel triple system constituting method by applying this method to a small-scale processor such as a microcomputer, by providing a series-data transmission interface and fault decision circuit.
CONSTITUTION: Input data to microcomputers 111 to 113 are collected and edited from controlled unit 130 via input-output interface 120. If a dissidence among input data is found through collation, they are made to coincide mutually following the fixed procedure. Next, respective computers 111 to 113 perform control logical operation and their results are compared with those of other systems. As a result, a fualt decision signal of "0" in case of the coincidence of output data or "1" in case of dissidence. On the basis of a status display signal in input data, it is discriminated whether or not there is a system recovering from its fault and when there is not, output data are sent to interface 120. When there is such a system, a decision on whether or not data collation results with other system agree is made; and in case of coincidence, they are outputted to interface 12 and in case of dissidence, an abnormality signal is outputted, thereby stopping the control.
COPYRIGHT: (C)1980,JPO&Japio
JP53090410A 1978-07-26 1978-07-26 Parallel triple system configuration method for computer system Expired JPS5931738B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53090410A JPS5931738B2 (en) 1978-07-26 1978-07-26 Parallel triple system configuration method for computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53090410A JPS5931738B2 (en) 1978-07-26 1978-07-26 Parallel triple system configuration method for computer system

Publications (2)

Publication Number Publication Date
JPS5518729A true JPS5518729A (en) 1980-02-09
JPS5931738B2 JPS5931738B2 (en) 1984-08-03

Family

ID=13997805

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53090410A Expired JPS5931738B2 (en) 1978-07-26 1978-07-26 Parallel triple system configuration method for computer system

Country Status (1)

Country Link
JP (1) JPS5931738B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6019288A (en) * 1983-07-14 1985-01-31 Meidensha Electric Mfg Co Ltd Synchronous processing system of dual connection type computer system
JPS6139138A (en) * 1984-07-31 1986-02-25 Nec Corp Multiplexing system
JPS6158050A (en) * 1985-04-19 1986-03-25 Hitachi Ltd Abnormality detector of multi-processing system
JPH0319069A (en) * 1989-06-16 1991-01-28 Nec Corp Diagnostic system for abnormality of multiprocessor
JPH04218862A (en) * 1991-02-08 1992-08-10 Hitachi Ltd Processing method for processing system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6019288A (en) * 1983-07-14 1985-01-31 Meidensha Electric Mfg Co Ltd Synchronous processing system of dual connection type computer system
JPS6139138A (en) * 1984-07-31 1986-02-25 Nec Corp Multiplexing system
JPS6158050A (en) * 1985-04-19 1986-03-25 Hitachi Ltd Abnormality detector of multi-processing system
JPH0319069A (en) * 1989-06-16 1991-01-28 Nec Corp Diagnostic system for abnormality of multiprocessor
JPH04218862A (en) * 1991-02-08 1992-08-10 Hitachi Ltd Processing method for processing system

Also Published As

Publication number Publication date
JPS5931738B2 (en) 1984-08-03

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