JPS5495145A - System check system - Google Patents

System check system

Info

Publication number
JPS5495145A
JPS5495145A JP298378A JP298378A JPS5495145A JP S5495145 A JPS5495145 A JP S5495145A JP 298378 A JP298378 A JP 298378A JP 298378 A JP298378 A JP 298378A JP S5495145 A JPS5495145 A JP S5495145A
Authority
JP
Japan
Prior art keywords
cpus
output
circuits
malfunction
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP298378A
Other languages
Japanese (ja)
Other versions
JPS5916304B2 (en
Inventor
Jun Miyazaki
Kozo Fujita
Kanji Okujima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP53002983A priority Critical patent/JPS5916304B2/en
Publication of JPS5495145A publication Critical patent/JPS5495145A/en
Publication of JPS5916304B2 publication Critical patent/JPS5916304B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To improve a system reliablity by providing a logical operation element for inter-microprocessor monitor and control to give a constitution where the processing and the countermeasure for malfunction can be performed rapidly.
CONSTITUTION: In the system where microprocessors μ-CPUs 7 and 8 are operated, coincidence decision circuits 9 and 10 and FF 11 which is set and reset by the output of circuits 9 and 10 are provided between data busses C and C' of μ-CPUs 7 and 8, and the output of FF 11 is connected to monitoring flag terminals F1 and F2 of μ-CPUs 7 and 8 respectively. Then, the output of circuits 9 and 10 is monitored by FF 11; and when the control direction of one of circuits 9 and 10 becomes reverse to normal-state conditions, the operation of FF 11 is inverted to communicate malfunction to μ-CPUs 7 and 8 by the output of FF 11, thereby controlling so that malfunction can be removed.
COPYRIGHT: (C)1979,JPO&Japio
JP53002983A 1978-01-13 1978-01-13 System check method Expired JPS5916304B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53002983A JPS5916304B2 (en) 1978-01-13 1978-01-13 System check method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53002983A JPS5916304B2 (en) 1978-01-13 1978-01-13 System check method

Publications (2)

Publication Number Publication Date
JPS5495145A true JPS5495145A (en) 1979-07-27
JPS5916304B2 JPS5916304B2 (en) 1984-04-14

Family

ID=11544596

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53002983A Expired JPS5916304B2 (en) 1978-01-13 1978-01-13 System check method

Country Status (1)

Country Link
JP (1) JPS5916304B2 (en)

Also Published As

Publication number Publication date
JPS5916304B2 (en) 1984-04-14

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