JPS553049A - Sequence controller - Google Patents

Sequence controller

Info

Publication number
JPS553049A
JPS553049A JP7523878A JP7523878A JPS553049A JP S553049 A JPS553049 A JP S553049A JP 7523878 A JP7523878 A JP 7523878A JP 7523878 A JP7523878 A JP 7523878A JP S553049 A JPS553049 A JP S553049A
Authority
JP
Japan
Prior art keywords
time
ram6
rom4
ram5
memorized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7523878A
Other languages
Japanese (ja)
Inventor
Isao Hatano
Yoshio Kushihashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP7523878A priority Critical patent/JPS553049A/en
Publication of JPS553049A publication Critical patent/JPS553049A/en
Pending legal-status Critical Current

Links

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  • Testing And Monitoring For Control Systems (AREA)

Abstract

PURPOSE:To secure emission of the alarm in case the normal sequence control becomes impossible for the controlled unit due to some fault. CONSTITUTION:ROM4, RAM5, RAM6, input circuit 7 and output circuit 8 are connected to CPU2 via data bus 3. CPU2 performs the data transfer for the register based on the program composed of the main routine memorized in ROM4 and the timer interruption process routine as well as the control for input/output circuits 7 and 8. The maximum time required for the operation of all steps of the controlled unit is set and memorized in RAM5 and then compared with the time counted at RAM6 with every step. And when a coincidence is secured between the maximum set time and the counted time, the occurrence of the fault is decided to emit the alarm.
JP7523878A 1978-06-20 1978-06-20 Sequence controller Pending JPS553049A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7523878A JPS553049A (en) 1978-06-20 1978-06-20 Sequence controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7523878A JPS553049A (en) 1978-06-20 1978-06-20 Sequence controller

Publications (1)

Publication Number Publication Date
JPS553049A true JPS553049A (en) 1980-01-10

Family

ID=13570431

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7523878A Pending JPS553049A (en) 1978-06-20 1978-06-20 Sequence controller

Country Status (1)

Country Link
JP (1) JPS553049A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5775315A (en) * 1980-10-29 1982-05-11 Fanuc Ltd Numerical control system
JPS57169809A (en) * 1981-04-13 1982-10-19 Omron Tateisi Electronics Co Programmable logic controller
JPS57189205A (en) * 1981-05-15 1982-11-20 Toyota Motor Corp Sequence controller

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5775315A (en) * 1980-10-29 1982-05-11 Fanuc Ltd Numerical control system
JPS57169809A (en) * 1981-04-13 1982-10-19 Omron Tateisi Electronics Co Programmable logic controller
JPS57189205A (en) * 1981-05-15 1982-11-20 Toyota Motor Corp Sequence controller

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