JPS5622149A - Monitoring system for electronic computer system - Google Patents

Monitoring system for electronic computer system

Info

Publication number
JPS5622149A
JPS5622149A JP9846379A JP9846379A JPS5622149A JP S5622149 A JPS5622149 A JP S5622149A JP 9846379 A JP9846379 A JP 9846379A JP 9846379 A JP9846379 A JP 9846379A JP S5622149 A JPS5622149 A JP S5622149A
Authority
JP
Japan
Prior art keywords
program
monitor
sup
instruction
cpu1
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9846379A
Other languages
Japanese (ja)
Other versions
JPS6010666B2 (en
Inventor
Shinichi Endo
Kenji Umehara
Koji Miyajima
Yutaka Kumazawa
Yoshimasa Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP54098463A priority Critical patent/JPS6010666B2/en
Publication of JPS5622149A publication Critical patent/JPS5622149A/en
Publication of JPS6010666B2 publication Critical patent/JPS6010666B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To secure an easy follow-up to the increment of the monitor subject units, by providing the program to collect and monitor the processing contents of other processor plus the program to exchange the information collected among the monitor devices to the specific processor.
CONSTITUTION: CPU1 gives the control to CPU2WCPUn as the input/output device and via channel coupling unit CTCA along with installation of program PB, and possesses the read instruction to collect the processing contents of each CPU plus the test I/O instruction to monitor the action of the read instruction. To oppose this, program PC is provided to CPU2WCPUn to function as the input/outpot device of CPU1. Monitor device SUP receives the control as an input/output device via program PA of CPU1. Program PA contains the write instruction to transfer the informtion and the monitor information collected through program PB to the SUP plus the reply instruction to the interruption given from the SUP. As a result, the correspondence is possible without increasing the interface part of the SUP although the monitor subject units may be increased.
COPYRIGHT: (C)1981,JPO&Japio
JP54098463A 1979-07-31 1979-07-31 Computer system monitoring method Expired JPS6010666B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54098463A JPS6010666B2 (en) 1979-07-31 1979-07-31 Computer system monitoring method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54098463A JPS6010666B2 (en) 1979-07-31 1979-07-31 Computer system monitoring method

Publications (2)

Publication Number Publication Date
JPS5622149A true JPS5622149A (en) 1981-03-02
JPS6010666B2 JPS6010666B2 (en) 1985-03-19

Family

ID=14220377

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54098463A Expired JPS6010666B2 (en) 1979-07-31 1979-07-31 Computer system monitoring method

Country Status (1)

Country Link
JP (1) JPS6010666B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58211255A (en) * 1982-05-31 1983-12-08 Mitsubishi Electric Corp Controlling circuit
JPS61208147A (en) * 1985-03-12 1986-09-16 Meidensha Electric Mfg Co Ltd Abnormality monitor system for microcomputer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58211255A (en) * 1982-05-31 1983-12-08 Mitsubishi Electric Corp Controlling circuit
JPS61208147A (en) * 1985-03-12 1986-09-16 Meidensha Electric Mfg Co Ltd Abnormality monitor system for microcomputer

Also Published As

Publication number Publication date
JPS6010666B2 (en) 1985-03-19

Similar Documents

Publication Publication Date Title
JPS55112651A (en) Virtual computer system
ATE88821T1 (en) INTERRUPTION HANDLING IN A MULTIPROCESSOR COMPUTER SYSTEM.
SE7900139L (en) DATA PROCESSING SYSTEM WITH SEPARATE INPUT / OUTPUT UNIT
JPS5622149A (en) Monitoring system for electronic computer system
JPS56110169A (en) Multiprocessor processing system
JPS5764859A (en) Multi-processor system
EP0297892A3 (en) Apparatus and method for control of asynchronous program interrupt events in a data processing system
JPS5680722A (en) Interprocessor control system
JPS553047A (en) Microdiagnosis system
JPS5587220A (en) Interface controller
JPS54161854A (en) Input/output control system for information processor
JPS5424553A (en) Control system for data transfer
JPS5717058A (en) Control system of microprogram
JPS5547557A (en) Mutual monitoring method of multi computer system
JPS54145447A (en) Input-output control system
JPS5654564A (en) Multiple computer system
JPS5523523A (en) Trouble disgnostic system of electronic computer system
JPS5585940A (en) Processing system for interruption input
JPS5559526A (en) Inter-processor data exchange system
KARAVANOVA et al. Principles of the design of a command processor and an analysis of its operation
EP0278263A3 (en) Multiple bus dma controller
LUKE et al. Critical item product function specification for the Multiprocessor Shared Memory(MSM)[Final Report, May 1979- Nov. 1982]
JPS5677995A (en) Main memory monitor device
JPS55157059A (en) Microcomputer system
Aldabass Microprocessor based parallelled computers, their simulation and application to control problems