JPS56165332A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS56165332A
JPS56165332A JP6926580A JP6926580A JPS56165332A JP S56165332 A JPS56165332 A JP S56165332A JP 6926580 A JP6926580 A JP 6926580A JP 6926580 A JP6926580 A JP 6926580A JP S56165332 A JPS56165332 A JP S56165332A
Authority
JP
Japan
Prior art keywords
layer
bonding wire
semiconductor device
semiconductor chip
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6926580A
Other languages
Japanese (ja)
Inventor
Toshinori Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6926580A priority Critical patent/JPS56165332A/en
Publication of JPS56165332A publication Critical patent/JPS56165332A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/05075Plural internal layers
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To cut down the production cost of the subject semiconductor device by a method wherein the bonding wire consisting of Ag is bonded on the Au on a semiconductor chip electrode or on the surface layer of the Ag. CONSTITUTION:An Al layer 5, a Ti layer 4, a Pt layer 3 and a n Au layer 2 are successively evaporated on the semiconductor chip 7 covered by a silicon oxide film 6 to the thickness of 500Angstrom or more for the Au and 3,000Angstrom for the others, and the Ag bonding wire 1 of 10muphi-30muphi is connected to an Au electrode. Through these procedures, the bonding wire consisting of Ag can be connected in the same manner as an Au wire and the lower cost than the Au can be obtained.
JP6926580A 1980-05-23 1980-05-23 Semiconductor device Pending JPS56165332A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6926580A JPS56165332A (en) 1980-05-23 1980-05-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6926580A JPS56165332A (en) 1980-05-23 1980-05-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS56165332A true JPS56165332A (en) 1981-12-18

Family

ID=13397687

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6926580A Pending JPS56165332A (en) 1980-05-23 1980-05-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS56165332A (en)

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