JPS5740944A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5740944A
JPS5740944A JP55116656A JP11665680A JPS5740944A JP S5740944 A JPS5740944 A JP S5740944A JP 55116656 A JP55116656 A JP 55116656A JP 11665680 A JP11665680 A JP 11665680A JP S5740944 A JPS5740944 A JP S5740944A
Authority
JP
Japan
Prior art keywords
layer
lead wire
semiconductor device
bonding pad
intermetallic compound
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55116656A
Other languages
Japanese (ja)
Other versions
JPS6322063B2 (en
Inventor
Katsuro Hiraiwa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55116656A priority Critical patent/JPS5740944A/en
Publication of JPS5740944A publication Critical patent/JPS5740944A/en
Publication of JPS6322063B2 publication Critical patent/JPS6322063B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
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    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/48624—Aluminium (Al) as principal constituent
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    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the exfoliation of a lead wire, by a method wherein the bonding pad in a semiconductor device is composed of two Al layers interposing an alloy growth stopping layer. CONSTITUTION:The first Al layer 4, an alloy growth stopping layer 8 consisting of Al2O3, and a bonding pad 20 consisting of general sections 10 and the second Al layer 5 are formed on an Si substrate 1 through an SiO2 layer 2 to cover them with a phosphor silicate glass (PSG) layer 3 and then an Au lead wire 6 (7 is an intermetallic compound of Au and Al) is bonded. In this way, the weak intermetallic compound 7 will not advance beyond the layer 8, so that the lead wire will not be exfoliated and the reliability of a semiconductor will be improved.
JP55116656A 1980-08-25 1980-08-25 Semiconductor device Granted JPS5740944A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55116656A JPS5740944A (en) 1980-08-25 1980-08-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55116656A JPS5740944A (en) 1980-08-25 1980-08-25 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5740944A true JPS5740944A (en) 1982-03-06
JPS6322063B2 JPS6322063B2 (en) 1988-05-10

Family

ID=14692630

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55116656A Granted JPS5740944A (en) 1980-08-25 1980-08-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5740944A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0821418B2 (en) * 1987-06-29 1996-03-04 松下電器産業株式会社 Lead acid battery

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5119968A (en) * 1974-08-12 1976-02-17 Hitachi Ltd

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5119968A (en) * 1974-08-12 1976-02-17 Hitachi Ltd

Also Published As

Publication number Publication date
JPS6322063B2 (en) 1988-05-10

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