JPS56164431A - Control system for interrupting priority - Google Patents

Control system for interrupting priority

Info

Publication number
JPS56164431A
JPS56164431A JP6819680A JP6819680A JPS56164431A JP S56164431 A JPS56164431 A JP S56164431A JP 6819680 A JP6819680 A JP 6819680A JP 6819680 A JP6819680 A JP 6819680A JP S56164431 A JPS56164431 A JP S56164431A
Authority
JP
Japan
Prior art keywords
line
timer
address
module
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6819680A
Other languages
Japanese (ja)
Inventor
Kinichi Takeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6819680A priority Critical patent/JPS56164431A/en
Publication of JPS56164431A publication Critical patent/JPS56164431A/en
Pending legal-status Critical Current

Links

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  • Bus Control (AREA)

Abstract

PURPOSE: To make interrupting control at system operation flexibly, by changing the priority information when a timer overflows and changing the priority through the addition of a simple logical circuit, through the provision of the timer that counts up while an interruption request signal is produced.
CONSTITUTION: A request signal from each module connected to bus line and its request line, priority information and an inherent address of each module are discriminated at a bus line control logical section connected to the request line and bus line, and the module used next is decided. From this control logical section, an address is outputted to each module 1n and an address and selection signal are outputted to selecting signal output lines 25 and 7, and they are compared with the address of itself at a comparison circuit 8. Further, when an interruption request is made to a line 24 via an FF1, a timer 5 is operated and the value of a counter 2 is renewed via a gate circuit 4 when the timer 5 overflows, and an output having higher priority than that of a line 23 is given to the control logic section, allowing flexible interruption.
COPYRIGHT: (C)1981,JPO&Japio
JP6819680A 1980-05-22 1980-05-22 Control system for interrupting priority Pending JPS56164431A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6819680A JPS56164431A (en) 1980-05-22 1980-05-22 Control system for interrupting priority

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6819680A JPS56164431A (en) 1980-05-22 1980-05-22 Control system for interrupting priority

Publications (1)

Publication Number Publication Date
JPS56164431A true JPS56164431A (en) 1981-12-17

Family

ID=13366787

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6819680A Pending JPS56164431A (en) 1980-05-22 1980-05-22 Control system for interrupting priority

Country Status (1)

Country Link
JP (1) JPS56164431A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63211438A (en) * 1987-02-27 1988-09-02 Nec Corp Interruption control circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63211438A (en) * 1987-02-27 1988-09-02 Nec Corp Interruption control circuit

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