JPS57201925A - Input/output port selecting device - Google Patents

Input/output port selecting device

Info

Publication number
JPS57201925A
JPS57201925A JP8559181A JP8559181A JPS57201925A JP S57201925 A JPS57201925 A JP S57201925A JP 8559181 A JP8559181 A JP 8559181A JP 8559181 A JP8559181 A JP 8559181A JP S57201925 A JPS57201925 A JP S57201925A
Authority
JP
Japan
Prior art keywords
port
register
selecting
decoder
packages
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8559181A
Other languages
Japanese (ja)
Inventor
Yoshio Kondo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8559181A priority Critical patent/JPS57201925A/en
Publication of JPS57201925A publication Critical patent/JPS57201925A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0653—Configuration or reconfiguration with centralised address assignment

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To select an optional port easily by deciding a device port to be selected on the basis of values of a logical channel number and a channel number register group and setting up a port selecting register. CONSTITUTION:A port selecting register 2, a channel register group 4, a port type reading line 1, and an operation controlling part 6 are connected to a data bus 7. The upper 4 bits of the port selecting register 2 are decoded by a decoder 3 and outputs from the decoder 3 are connected to slot selecting lines for device port packages 5-1-5-4. An optional device port package is selected by the output of the decoder 3. The lower 4 bits of the port selecting register 2 form a port selecting signal, which is directly connected to the device packages 5-1-5-4 and decoded by the respective packages to select a magnetic disk device MSD connected to the corresponding device port.
JP8559181A 1981-06-05 1981-06-05 Input/output port selecting device Pending JPS57201925A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8559181A JPS57201925A (en) 1981-06-05 1981-06-05 Input/output port selecting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8559181A JPS57201925A (en) 1981-06-05 1981-06-05 Input/output port selecting device

Publications (1)

Publication Number Publication Date
JPS57201925A true JPS57201925A (en) 1982-12-10

Family

ID=13863055

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8559181A Pending JPS57201925A (en) 1981-06-05 1981-06-05 Input/output port selecting device

Country Status (1)

Country Link
JP (1) JPS57201925A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6071962U (en) * 1983-10-19 1985-05-21 富士フアコム制御株式会社 Operation mode setting device
JPS6152762A (en) * 1984-08-22 1986-03-15 Nippon Data General Kk Bus control gate array
WO1987006369A1 (en) * 1986-04-18 1987-10-22 Fanuc Ltd Method of assigning a board slot number
JPH04233622A (en) * 1990-07-19 1992-08-21 Internatl Business Mach Corp <Ibm> Personal computer which identifies driving mechanism
JPH04233623A (en) * 1990-07-20 1992-08-21 Internatl Business Mach Corp <Ibm> Personal computer which identifies attaching and removing type medium

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6071962U (en) * 1983-10-19 1985-05-21 富士フアコム制御株式会社 Operation mode setting device
JPS6152762A (en) * 1984-08-22 1986-03-15 Nippon Data General Kk Bus control gate array
WO1987006369A1 (en) * 1986-04-18 1987-10-22 Fanuc Ltd Method of assigning a board slot number
JPH04233622A (en) * 1990-07-19 1992-08-21 Internatl Business Mach Corp <Ibm> Personal computer which identifies driving mechanism
JPH04233623A (en) * 1990-07-20 1992-08-21 Internatl Business Mach Corp <Ibm> Personal computer which identifies attaching and removing type medium

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