JPS5789174A - Data processing control system - Google Patents
Data processing control systemInfo
- Publication number
- JPS5789174A JPS5789174A JP16616380A JP16616380A JPS5789174A JP S5789174 A JPS5789174 A JP S5789174A JP 16616380 A JP16616380 A JP 16616380A JP 16616380 A JP16616380 A JP 16616380A JP S5789174 A JPS5789174 A JP S5789174A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- inputted
- output
- logical circuit
- decoder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8053—Vector processors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Complex Calculations (AREA)
Abstract
PURPOSE:To place consecutive elements of a vector register in sequence of corresponding banks, also to prescribe a timing for accessing an element, and to initialize its prescription to an optional timing. CONSTITUTION:A processing instruction is inputted to a decoder 21, and an output of the decoder 21 is inputted to a setting logical circuit 22. To the circuit 22, an output of a controlling circuit 24 is inputted through a resetting logical circuit 23. An output of the circuit 22 is made to branch to 4, and each of them is inputted to A, D, G and H, that is to say, the first, fourth, seventh and eighth bits of a shift register 20. The controlling circuit 24 always controls an access state of a vector register, and when an idle access is detected, it is informed to the resetting logical circuit 23. The resetting circuit 23 which has received the information resets all the bits of the shift register 20, and also presses the setting logical circuit 22 to set the prescription again. The setting logical circuit 22 reads the contents by an output of the decoder 21 to which the instruction has been inputted.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16616380A JPS5789174A (en) | 1980-11-26 | 1980-11-26 | Data processing control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16616380A JPS5789174A (en) | 1980-11-26 | 1980-11-26 | Data processing control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5789174A true JPS5789174A (en) | 1982-06-03 |
Family
ID=15826236
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16616380A Pending JPS5789174A (en) | 1980-11-26 | 1980-11-26 | Data processing control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5789174A (en) |
-
1980
- 1980-11-26 JP JP16616380A patent/JPS5789174A/en active Pending
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