JPS57147730A - Bus control circuit - Google Patents

Bus control circuit

Info

Publication number
JPS57147730A
JPS57147730A JP3251081A JP3251081A JPS57147730A JP S57147730 A JPS57147730 A JP S57147730A JP 3251081 A JP3251081 A JP 3251081A JP 3251081 A JP3251081 A JP 3251081A JP S57147730 A JPS57147730 A JP S57147730A
Authority
JP
Japan
Prior art keywords
tristate
gate
enabled
timing
tristate gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3251081A
Other languages
Japanese (ja)
Inventor
Tetsuo Makino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3251081A priority Critical patent/JPS57147730A/en
Publication of JPS57147730A publication Critical patent/JPS57147730A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To prevent the output circuit of a tristate gate from deteriorating, by inhibiting >=2 tristate gates from being enabled at the same time by providing (n) units of tristate gates whose outputs are OR-wired. CONSTITUTION:The data output of a tristate gate 19, that of the 1st tristate gate 11, and that of the 2nd tristate gate 12 are wired on OR basis. When the 1st original enable signal 15 and 2nd original enable signal 21 both have logic[1], the 1st control signal 17 and 2nd control signal 23 both have logic[1]. Therefore, an enable signal 20 supplied from an NAND gate 24 to the 3rd tristate gate 19 at this time has logic[0], and the 3rd tristate gate 19 is enabled. The 1st tristate gate 11 is enabled from timing T7 to timing T9. Further, the 2nd tristate gate 12 is enabled from timing T12 to timing T14.
JP3251081A 1981-03-09 1981-03-09 Bus control circuit Pending JPS57147730A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3251081A JPS57147730A (en) 1981-03-09 1981-03-09 Bus control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3251081A JPS57147730A (en) 1981-03-09 1981-03-09 Bus control circuit

Publications (1)

Publication Number Publication Date
JPS57147730A true JPS57147730A (en) 1982-09-11

Family

ID=12360975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3251081A Pending JPS57147730A (en) 1981-03-09 1981-03-09 Bus control circuit

Country Status (1)

Country Link
JP (1) JPS57147730A (en)

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