JPS561576A - Light semiconductor device - Google Patents
Light semiconductor deviceInfo
- Publication number
- JPS561576A JPS561576A JP7711079A JP7711079A JPS561576A JP S561576 A JPS561576 A JP S561576A JP 7711079 A JP7711079 A JP 7711079A JP 7711079 A JP7711079 A JP 7711079A JP S561576 A JPS561576 A JP S561576A
- Authority
- JP
- Japan
- Prior art keywords
- recess
- optical fiber
- type region
- periphery
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4202—Packages, e.g. shape, construction, internal or external details for coupling an active element with fibres without intermediate optical elements, e.g. fibres with plane ends, fibres with shaped ends, bundles
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
- G02B6/4228—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements
- G02B6/423—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements using guiding surfaces for the alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Light Receiving Elements (AREA)
Abstract
PURPOSE:To exactly approach an optical fiber to a semiconductor light receiving element and easily position therebetween by forming a recess on the contacting surface of the optical fiber with the element formed with P-N junction and inserting the optical fiber at the end into the recess. CONSTITUTION:An N-type region and a guard ring 9 are formed to extend an operating depletion layer at the center on the back surface of a P-type Si substrate 8, an aluminum electrode 10 is mounted on the N-type region, and an oxide film 11 is coated on the periphery thereof. Then, a recess 12 for inserting an optical fiber 4 is formed at the portion confronting the N-type region on the surface of the substrate 8, a P<+>-type layer 13 is diffused on the surface including the recess 12, and an aluminum electrode 14 is coated on the periphery of the recess 12. In this manner a light receiving element 1 is formed, the N-type region is confronted with the conductive layer 16 formed on a ceramic substrate 15, and epoxy adhesive region 17 is filled in the space thereamong fixedly. Thereafter, they are connected as predetermined, an optical fiber 4 is inserted into the recess 12 on the surface of the element 1 with a transparent resin 22, and the periphery of the fiber 4 is molded with resin 24.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7711079A JPS561576A (en) | 1979-06-19 | 1979-06-19 | Light semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7711079A JPS561576A (en) | 1979-06-19 | 1979-06-19 | Light semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS561576A true JPS561576A (en) | 1981-01-09 |
Family
ID=13624636
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7711079A Pending JPS561576A (en) | 1979-06-19 | 1979-06-19 | Light semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS561576A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5916389A (en) * | 1982-07-19 | 1984-01-27 | Toshiba Corp | Bidirectional optical module and device thereof |
-
1979
- 1979-06-19 JP JP7711079A patent/JPS561576A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5916389A (en) * | 1982-07-19 | 1984-01-27 | Toshiba Corp | Bidirectional optical module and device thereof |
JPS6259914B2 (en) * | 1982-07-19 | 1987-12-14 | Tokyo Shibaura Electric Co |
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