JPS56104442A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS56104442A
JPS56104442A JP736480A JP736480A JPS56104442A JP S56104442 A JPS56104442 A JP S56104442A JP 736480 A JP736480 A JP 736480A JP 736480 A JP736480 A JP 736480A JP S56104442 A JPS56104442 A JP S56104442A
Authority
JP
Japan
Prior art keywords
region
type
semiconductor device
substrate
junction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP736480A
Other languages
Japanese (ja)
Inventor
Masao Kachi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP736480A priority Critical patent/JPS56104442A/en
Publication of JPS56104442A publication Critical patent/JPS56104442A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To obtain the high withstand voltage characteristics of the semiconductor device by forming different conductivity type regions on both the front surface and the back surface of a high specific resistance substrate to thus form a P-N junction, and forming a mesa groove having a passivation layer terminating at the boundary between one conductivity type region and the substrate region. CONSTITUTION:An N type region 3 and a P type region 4 are selectively diffused by utilizing an oxide film on the back surface of the high specific resistance semiconductor substrate 1 to form the P-N junction 5 therebetween, an N<+> type collector region 6 and an N<+> type emitter region 7 are selectively diffused again, the mesa groove 8 is terminated at the boundary between the region 1 and the region 4, and glass or silicon rubber or the like 9 is filled therein. Thus, the semiconductor device having high withstand voltage and stable properties can be obtained.
JP736480A 1980-01-23 1980-01-23 Semiconductor device Pending JPS56104442A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP736480A JPS56104442A (en) 1980-01-23 1980-01-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP736480A JPS56104442A (en) 1980-01-23 1980-01-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS56104442A true JPS56104442A (en) 1981-08-20

Family

ID=11663906

Family Applications (1)

Application Number Title Priority Date Filing Date
JP736480A Pending JPS56104442A (en) 1980-01-23 1980-01-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS56104442A (en)

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